天堂寨作文400字4篇
天堂寨作文400字
天堂寨作文400字
天堂寨作文400字一：美丽的天堂寨（423字）今天，是一个快乐的星期五，我要和爸爸妈妈一起去一个美丽的地方――天堂寨。
天堂寨在金寨县的东南方，那里峰峰有溪水环绕，水道随山峰弯曲回转。
天堂寨旁边有一座山，叫霍山，霍山和武夷山不同，霍山只有一个峰，叫白马峰，从山下往上看就像一只昂首挺胸的白马正在奔跑。
第二天，我起的很早，起来时，才五点多，连爸爸妈妈都没醒呢！我悄悄的去洗脸、刷牙，洗漱过后，我发现了一个很奇妙的东西，原来呀霍山的早晨也有云海呀！我赶快把爸爸妈妈叫醒，让他们也看看云海!
吃完饭，我们一起去爬山，我们看到了霍山的五道瀑布，最长的是在索道中途时往右边看才能看到的啊！
后来，我们来到了白马峰，我和爸爸、妈妈、叔叔、阿姨、哥哥、姐姐在山峰一起大声呼唤：“大山，你好！”
很快，快乐的一天又过去了，新的一天又要来到了。
最后一天，我们去大侠谷玩，大侠谷的山路非常险，一不小
心就会掉到山下去。大侠谷的水非常清，清的能可能见溪低的沙石。
我们的旅游结束了，这次旅游让我了解了金寨县，让我了解了天堂寨!
天堂寨作文400字二：天堂寨之旅（478字）去年暑假期间，我和爸爸妈妈到天堂寨去旅游。天堂寨坐落在安徽省六安市境内附近，是个很有名的旅游景点，我怀着好奇和憧憬的心情去了天堂寨。
一路上，外面的空气香风习习令人心旷神怡，那树木更是郁郁苍苍。大约九点左右我们到了天堂寨，寨门是多么威武。一进门，就看见了风景宜人的自然景观，那可以用二十个字来形容：重重叠叠山，曲曲环环路，叮叮咚咚泉，高高下下树。
这儿的建筑都模仿着古代的风格，饭店高高挂起的酒幌子随风飘荡好像在招揽着顾客，使人一下子就记起杜牧的“水村山郭酒旗风”的诗句来，曲曲折折的石板路链接每一个店铺，一个个古玩店勾起了我的兴趣我对古玩虽一窍不通，但也细细观赏起来。那些精巧雕刻，造型奇特陶器，竟使我看得入神了，游兴也越来越浓。转着转着，一个卖乐器的商店映入我的眼帘，我兴奋地走了进去，一眼我就看中了一支笛子。爸爸给我买了一支，我一边走一边吹，发现上面写了几个字：一笛在手，百鸟争鸣。怪不得，我一吹鸟儿就跟着叫呢！夕阳西下，晚霞满天提醒我们该回家了。还有几个景点还没转到，我有些恋恋不舍，我希望今年暑假的时候再和同学们一起去看一看，再去领略那天堂般的境界！
天堂寨作文400字三：游天堂寨之白马大峡谷（464字）这是我们旅途的第三天，我们在半山腰下了车。
等人到齐后，我们向滑索走去，到了栏边。我怀着一颗强烈的好奇心往下看，顿时胆战心惊：那地下是无底深渊，万一滑索……勇敢的大人都一个一个地滑过去了，看着他们一咬牙“磁”的一下就过去了，但我总是忐忑不安，生怕出事情。到我了，我一咬牙，走上了台阶，睁开了眼，青翠欲滴的一棵棵大树密密麻麻地分布在河岸的两旁，像一个个忠诚伟岸的卫士，守卫着一条清澈见底的小溪流。我见过碧绿的西湖，也见过无边的大海，可从没见过这么清的溪流。它的水真清呀，清得想让你去喝一口；它的水真美呀！蓝天、白云、绿树…全倒映在水中，形成了一幅大自然的画。到了站台，我意犹未尽，我真希望时间能够定格在那一美好的瞬间。下了滑索，我们开始沿着溪边台阶向山下走去，边上的树木纵横交错，形成了一条篱笆，防止我们掉下去。密密的枝叶挡住了强烈的太阳，让我们的旅途一路绿荫，哗哗的溪水声更是一支奏响在山间的美妙乐曲。听导游说，这山上一共有“六顺”，分别是路顺、天顺、情顺、福顺、气顺、心顺。
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作文来 源星& 火 资源 w ww. J g ZY w.c O m大自然的文字是无奇不有的。 　 　　它们有的能够提示人们天气的变化，有的能够启迪我们的智慧，有的能够让我们上一堂奇妙的生物课……这些大自然的文字只有仔细观察的人才能了解其中的奥秘，粗枝大叶的人什么也看不懂！ 　 　 　　你看，这轻纱般的薄雾在清晨出现，就预示着今天将会是一个阳光明媚的好日子；可如果在晚上出现，那就会预示着阴雨绵绵。看来，雾也是个气象员。 　 　 　　瞧，蝌蚪在水中游泳，是不是像一个个会移动的逗号，这一群群可爱的逗号告诉人们，已春回大地；美丽五彩的虹，是否像一座缤纷的桥梁，这“七彩桥”正衬托着夏日火辣的热情；一片火红的枫叶在瑟瑟风中摇曳，真像一只拍红了的小手，枫叶正在向大家讲述秋天的豪爽性情；皑皑的白雪覆盖着神州大地，这套雪白而又柔软的棉被见证着冬天的“冷酷”！看，这奇妙的现象向人们了一年四季的变化，是不是很有趣呀！ 　 　 　　作为21世纪的小学生，我们不应该“一心只读圣贤书”，也应该到田野中去散散步，触摸勃勃生机的大自然。去大自然中探索，去发现大自然中隐藏的奥秘！ [作文由整理发布,版权归原作者所有。]
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音乐让我沉醉　想不到，你也有伤心的一面　除害事件　李老师(转载)　无解的谜[3]——第一次激战　
-------- |Patent EP - Two transistor nor device - Google PatentsEPApplicationEPPCT/USAug 17, 2005Oct 14, 2003Nov 22, 2002, , , , , , , EP , EP , EP-A1-1563543, EP, EP, EP, EP, PCT/, PCT/US/, PCT/US/, PCT/US/3/032782, PCT/US/3/32782, PCT/US, PCT/US, PCT/US, PCT/US, PCT/US3/032782, PCT/US3/32782, PCT/US3032782, PCT/US332782, , , , ,
(8) , Two transistor nor device
EP &(text from )&
A NOR gate includes is constructed with two asymmetric FinFET type transistors (801, 802) instead of the conventional four-transistor NOR gate. The reduction in the number of transistors from four down to two allows for significant improvements in integrated semiconductor circuits.
WHAT IS CLAIMED IS:
1. A NOR gate comprising: a first FinFET (801) including first and second independently controllable gate regions (822, 823), a source region (821), and a drain region (820); a second FinFET (802) including first and second independently controllable gate regions (832, 833), a source region (831), and a drain region (830); a first input Une of the NOR gate connected to the first gate region (822) of the first FinFET (801) and the first gate region (832)of the second FinFET (802); a second input line of the NOR gate connected to the second gate region (823) of the first FinFET (801) and the second gate region (833) of the second FinFET (802); and an output line of the NOR gate connected to the source (820) of the first FinFET (801) and the drain (830) of the second FinFET (802).
2. The NOR gate of claim 1, wherein the first gate regions of the first and second FinFETs are doped with n-type impurities.
3. The NOR gate of claim 2, wherein the second gate regions of the first and second
FinFETs are doped with p-type impurities.
4. The NOR gate of claim 1, wherein the first and second FinFETs are the only transistors included in the NOR gate.
5. An integrated semiconductor device including a plurality of FinFETs (801, 802), the device characterized in that: at least some of the plurality of FinFETs being arranged as pairs of FinFETs that define logic NOR gates.
6. The integrated semiconductor device of claim 5, wherein the pairs of FinFETs include: a first FinFET (801) including first and second independently controllable gate regions (822, 823), a source region (821), and a drain region (820); and a second FinFET (802) including first and second independently controllable gate regions (832, 833), a source region (831), and a drain region (830); a first input Une connected to the first gate region (822) of the first FinFET (801) and the first gate region (832) of the second FinFET (802);
a second input line connected to the second gate region (823) of the first FinFET (801) and the second gate region (833) of the second FinFET (802); and an output line connected to the source (821) of the first FinFET (801) and the drain (830) of the second FinFET (802).
7. A logic NOR circuit comprising: a first double-gate transistor (801); and a second double-gate transistor (802), wherein an output signal coupled to the first and second transistors reflects a logical NOR operation of two input signals applied to the first and second transistors.
8. The logic NOR circuit of claim 7, wherein the first and second double-gate transistors are FinFETs.
9. The logic NOR circuit of claim 7, wherein the first and second double-gate transistors each include: a first gate region (822 or 832); a second gate region (823 or 833) configured to be controllable independently of t a source region (821 or 831); and a drain region (820 or 830).
10. The logic NOR circuit of claim 9, wherein the first gate region is doped with n-type impurities.
TWO TRANSISTOR NOR DEVICE
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates generally to semiconductor manufacturing and semiconductor devices and, more particularly, to double gate metal-oxide semiconductor field-effect transistors (MOSFET).
B. Description of Related Art Transistors, such as MOSFETs, are the core building block of the vast majority of semiconductor devices. Some semiconductor devices, such as high performance processors, can include millions of transistors. For these devices, decreasing transistor size, and thus increasing transistor density, has traditionally been a high priority in the semiconductor manufacturing area.
Conventional MOSFETs have difficulty scaling below 50nm fabrication processing. To develop sub- 50nm MOSFETs, double-gate MOSFETs have been proposed. In several respects, the double-gate MOSFETs offer better characteristics than the conventional bulk silicon MOSFETs. These improvements arise because the double-gate MOSFET has a gate electrode on both sides of the channel, rather than only on one side as in conventional MOSFETs. When there are two gates, the electric field generated by the drain is better screened from the source end of the channel. Also, two gates can control roughly twice as much current as a single gate, resulting in a stronger switching signal.
Transistors on a semiconductor device are often connected into groups that implement higher level logical gates. One frequently used logical gate is the NOR gate. Conventionally, four transistors, such as four double-gate MOSFETs, are used to create a NOR gate.
It would be desirable to more efficiently implement a logical gate such as a NOR gate, as this would increase the overall efficiency of the semiconductor device.
SUMMARY OF THE INVENTION Implementations consistent with the present invention include a NOR gate implemented with only two transistors.
One aspect of the invention is directed to an integrated semiconductor device. The device includes a number of asymmetric FinFETs, at least some of the FinFETs being arranged as pairs of FinFETs that define logic NOR gates.
A second aspect of the invention is directed to a logic NOR gate consisting of a first double-gate transistor and a second double-gate transistor. An output signal coupled to the first and second transistors reflects a logical NOR operation of two input signals coupled to the first and second transistors.
BRIEF DESCRIPTION OF THE DRAWINGS Reference is made to the attached drawings, wherein elements having the same reference number designation may represent like elements throughout.
Fig. 1 is a schematic diagram that illustrates a top-level view of a FinFET consistent with princip
Figs. 2-7 are schematic diagrams taken along the line A-A' in Fig. 1 that illustrate a method of forming an asymmetric FinFET; Fig. 8 is a schematic diagram that illustrates a top view of a NOR gate constructed in a manner consistent with t and
Fig. 9 is a diagram illustrating deposition of polysilicon over two gate portions of a FinFET.
BEST MODE FOR CARRYING OUT THE INVENTION The following detailed description of the invention refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify the same or similar elements. Also, the following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims and equivalents.
Two transistors are connected together to implement a NOR gate. Each one of the transistors may be an asymmetric FinFET having two separately addressable gates. ASYMMETRIC FinFET
A FinFET, as the term is used herein, refers to a type of double-gate MOSFET in which a conducting channel is formed in a vertical Si "fin" controlled by a self-aligned double-gate. FinFETs are known in the art. Although conventional FinFETs are typically described as "double-gate" MOSFETs, the two gates are electrically connected and thus form a single logically addressable gate.
Fig. 1 is a top-level view of a FinFET 100 consistent with principles of the invention. FinFET 100 includes a source region 101, a drain region 102, and a channel region 103. The channel region 103 includes the transistor's fin, as described with respect to Fig. 2, below. Unlike conventional FinFETs, in which both sides of the gate are electrically connected together, FinFET 100 may additionally include two addressable gates, labeled as gates 104 and 105. The gates may further be asymmetrically doped. Gate 104 may, for example, be implanted with n-type dopants (e.g., As+ or P+) and gate 105 may be implanted with p-type dopants (e.g., B or BF2), as described in more detail below.
Figs. 2-7 are cross-sectional views taken along the line A-A' in Fig. 1. Figs. 2-8 each illustrate steps in the manufacturing process of FinFET 100. Referring to Fig. 2, FinFET 100 may be a silicon on insulator (SOI) device that includes a silicon substrate 210 and a buried oxide (BOX) layer 220 disposed on the silicon substrate. Substrate 210 and layer 230 may alternatively comprise germanium, metals, or combinations of such materials, such as silicon- germanium. Buried oxide layer 220 may be formed on silicon substrate 210 in a conventional manner. Buried oxide layer 220 may range, for example, from approximately 200 nm to 400 nm in thickness. A silicon layer may be disposed on BOX layer 220 and etched to create the source, drain, and fin 225
(source and drain not shown in Fig. 2). Alternatively, source/drain regions 101 and 102 may be formed by depositing silicon and etching the silicon after the fin 225 is formed. In one implementation, fin 225 may range from, for example, approximately 5 nm to about 25 nm in width. Before etching fin 225, a Si3N layer 230 may be deposited via chemical vapor deposition (CVD) on fin 225. Layer 230 may alternatively be a Si02 layer. Layer 230 protects fin 225 during the fabrication process, and may be, for example, deposited to a thickness ranging from about 20-50 nm.
By oxidizing the silicon surface of fin 225, gate dielectric layers 235 may be grown on the side surface of fin 225. Gate dielectric layers 235 may be as thin as 0.8 nm to 2 nm in width.
Referring to Fig. 3, polysilicon spacers 240 may next be formed around fin 225 (and around gate dielectric layers 235 and layer 230) using conventional deposition and etching techniques.
Polysilicon spacers 240 may then be implanted with an n-type dopant using a tilted implant process (Fig. 4). The dopant may be, for example, As+ or P+, and may be implanted using a 3-6 keV (for P+) or 12-15 keV (for As"1} ion beam at a tilt angle of between 15 and 45 degrees. Because of the presence of fin structure
225, including gate dielectric layers 235 and layer 230, the n-type dopant will be largely blocked from entering one side of polysilicon spacers 240 (e.g., as illustrated of the right side of Fig. 4).
Following the n-type dopant implantation, polysilicon spacers may be implanted with a p-type dopant using a tilted implant process. The ion beam of the implant process may be tilted at a complementary angle to that described with respect to Fig. 4. The dopant may be, for example, B or BF2, and may be implanted using a
<p num="p keV (for B) or 4-8 keV (for BF2) ion beam at a tilt angle of between 15 and 45 degrees. Because of the presence of fin structure 225, including gate dielectric layers 235 and layer 230, the p-type dopant will be largely blocked from entering one side of polysilicon spacers 240 (e.g., as illustrated on the left side in Fig. 5).
Accordingly, the two polysilicon spacers 240 will be asymmetrically doped with n-type and p-type dopants. One of ordinary skill in the art will appreciate that the order of the steps shown in Figs. 4 and 5 could be readily reversed.
Referring to Fig. 6, an undoped polysilicon layer 250 may then be deposited on FinFET 100.
Polysilicon layer 250 will form the gates of FinFET 100. Layer 250 may be deposited via, for example, CVD to a depth of approximately 100 nm. After depositing the polysilicon layer 250, FinFET 100 may be planarized such that layer 250 is substantially planar with the top surface of layer 230, as illustrated in Fig. 7A. This yields two electrically unconnected polysilicon layers, labeled as layers 251 and 252. FinFET 100 may then be annealed to create fully-silicided polysilicon layers 251 and 252, as illustrated in Fig. 7B. Layers 251 and 252 may be connected to gate pads 104 and 105 and may be independently controlled. -Other processes for creating asymmetric FinFETs, such as those illustrated in Fig. 7B may alternatively be employed. For example, the tilt implant process described with respect to Figs. 4 and 5 may be performed after polysilicon gate material is deposited and planarized. In each case, the resulting structure includes the two separately controllable gates, as illustrated in Fig. 7B.
NOR GATE A NOR gate is a logic gate that is frequently used in integrated circuits. A NOR gate outputs a value based on two or more input signals. Conventionally, NOR gates are constructed using four transistors.
The logic for a two-input NOR gate is shown below in Table I.
Consistent with an aspect of the invention, a NOR gate is constructed using two asymmetric FinFETs, such as FinFETs 100. Fig. 8 is a top view of NOR gate 800 constructed in a manner consistent with the present invention. NOR gate 800 may be located in an integrated semiconductor device.
NOR gate 800 includes two FinFETs, labeled as FinFETs 801 and 802. Each of FinFETs 801 and 802 are similar to FinFET 100. In particular, FinFET 801 includes a drain region 820, a source region 821, a first gate 822, a second gate 823, and a channel (fin) region 824. FinFET 802 similarly includes a drain region 830, a source region 831, a first gate 832, a second gate 833, and a channel region 834. First gates 822 and 832 may be doped with n-type impurities while second gates 823 and 833 may be doped with p-type impurities.
As shown in Fig. 8, gates 822 and 832 may be el gates 823 and 833 may be el and source 821 may be electrically connected to drain 830. Drain 820 may be connected to ground, and source 831 may be connected to a power supply 810. In operation, the input signal lines to NOR gate 800 (labeled as inputs "A" and "B" in Fig. 8) are applied to the first and second pairs of electrically connected gates. Thus, input signal line A may connect to gates 823 and 833, while input signal Une B may connect to gates 822 and 832. The output signal of NOR gate 800 is taken between source 821 and drain 830. The output value depends on inputs A and B according to the logic shown in Table I. ADDITIONAL DISCLOSURE
In certain situations, it may be desirable to create integrated circuits that include both conventional FinFETs, which have a single connected double-gate, and the asymmetric FinFET described above, which has two separately addressable gates. In these situations, all of the FinFETs may be initially created as described
above in Figs. 2-7. An additional selective epitaxial growth step may then be applied to those of the FinFETs that are to be conventional FinFETs.
Fig. 9 illustrates deposition of polysilicon over the two gate portions of a FinFET 900. Polysilicon layer 901 may be selectively formed on those of the FinFETs in the integrated circuit that are designed to have a single connected gate structure. Polysilicon layer 901 may be, for example, formed to a depth of 100 nm by selective epitaxial growth.
In other situations, it may be desirable to form a Schottky type source/drain formation for the FinFET. This can be accomplished using a damascene approach in which the nitride layer over the fin is used as an etch-stop. Referring to Fig. 9, polysilicon layer 901 may be used as an etch stop to etch a trench over nitride layer 930. After removing the silicon, a trench is left over the source/drain area. Metal can then be deposited and polished using nitride layer 930 as a stop layer. The metal forms Schottky contacts with the silicon channel.
CONCLUSION A NOR gate is described above that can be implemented with two FinFET type transistors instead of the conventional four transistors. Thus, the NOR gate described herein uses half the conventional number of transistors, thereby providing significant improvements in gate density and in overall functionality of the integrated silicon device.
In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention.
However, the present invention can be practiced without resorting to the specific details set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention.
The dielectric and conductive layers used in manufacturing a semiconductor device in accordance with the present invention can be deposited by conventional deposition techniques. For example, metalUzation techniques, such as various types of chemical vapor deposition (CVD) processes, including low pressure chemical vapor deposition (LPCVD) and enhanced chemical vapor deposition (ECVD) can be employed.
The present invention is applicable in the manufacturing of semiconductor devices and particularly in semiconductor devices with design features of lOOnm and below, resulting in increased transistor and circuit
speeds and improved reUabiUty. The present invention is appUcable to the formation of any of various types of semiconductor devices, and hence, details have not been set forth in order to avoid obscuring the thrust of the present invention. In practicing the present invention, conventional photoUthographic and etching techniques are employed and, hence, the details of such techniques have not been set forth herein in detail.
Only the preferred embodiments of the invention and a few examples of its versatiUty are shown and described in the present disclosure. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of modifications within the scope of the inventive concept as expressed herein.
1 *See references of International Classification, , , , Cooperative Classification, , , , , , , European ClassificationH01L27/092F, H01L27/088F, H01L27/12B, H01L29/423D2B8, H01L27/092, H01L27/088, H01L29/78SAKDesignated contracting states:Kind code of ref document: A1Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TRAXRequest for extension of the european patent toCountries concerned: ALLTLVMK17PRequest for examination filedEffective date: RBVDesignated contracting states (correction):Designated state(s): DE FR GBDAXRequest for extension of the european patent (to any country) deleted17QFirst examination reportEffective date: RAP1Transfer of rights of an ep published applicationOwner name: GLOBALFOUNDRIES, INC.18RRefusedEffective date: RotateData provided by IFI CLAIMS Patent Services}