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联想G485-LA8681PAMD独显
ABCDE11Compal Confidential2 2PAWGE Schematics DocumentAMD APU Zacate-FT1 + FCH Hudson-M3L + GPU RobsonXT3 REV:1.0344Security Classification Issued Date Compal Secret DataDeciphered DateCompal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C DCover PageSize B Date: Document NumberLA8681PTuesday, November 29, 2011ERev 1.0 1 of 48SheetABCDECompal confidentialFile Name : PAWGEQIWG5LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B1QIWG6LVDS Conn.page 221AMD Brazos APUCRT Conn.page 24Memory BUS(DDRIII) 200pin DDRII-SO-DIMM X2Single Channel1.5V DDRIII 1333BANK 0, 1, 2, 3page 8,9AMDRosbon XT_M2 VRAM 64*16 DDR3*4page 15 ~ 21HDMI Conn.page 23FT1 BGA 413-Ball 19mm x 19mmpage 5,6,7LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B LS7984P LED/B LS7985P ODD/Bx4 PCI-E GPP GEN2 x4 UMI Gen. 2 2Channel Speakerpage 272Hudson M3LBGA 656-Ball 23mm x 23mm 4 * x1 PCI-E 1.0 WLAN &WiMax GIGA LAN RTLpage 25,263Audio CodecAZALIA CX20671page 27Internal MIC2page 27Audio JacksStereo HeadPhone Output Microphone Input10*USB2.0page 29page 10,11,12,13,142*SATA serialCMOS Camera page 22 BlueTooth CONN page 28 USB PORT 2.0 x2(Left)page 33LPC BUSUSB PORT 3.0 x2(Right) WLAN/WiMAXpage 34SPI ROMpage 11ECENE KB9012page 303PCI Express Mini card Slot 1WLAN/WiMAX page 29USB(WiMAX) PCI-E(WLAN)Card ReaderRealtek RTS5178 SD/MMC Daoughter boardInt.KBDpage 32Touch Padpage 32SATA3.0 HDD CONN page 28 Thermal Sensor4EMC1403 page 29SATA ODD CONN page 284Security Classification Issued Date Compal Secret DataDeciphered DateCompal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C DBlock DiagramsSize B Date: Document NumberLA8681PTuesday, November 29, 2011ERev 1.0 2 of 48SheetABCDEVoltage RailsPower Plane VIN B+ +APU_CORE +APU_CORE_NB1Description Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU (0.7-1.2V) 1.0V switched power rail 1.5V power rail for CPU VDDIO and DDRIII 0.75VS switched power rail for DDR terminator 1.0V switched power rail for NB VDDC & VGA 1.1VS switched power rail 1.8V switched power rail 3.3V always on power rail 3.3V power rail for LAN 3.3V switched power rail 5V always on power rail 5V switched power rail VSB always on power rail RTC power 1.1V always on power railS1 N/A N/A ON ON ON ON ON ON ON ON ON ON ON ON ON ONS3 N/A N/A OFF OFF ON OFF OFF OFF OFF ON OFF ON OFF ON ON ONS5 N/A N/A OFF OFF OFF OFF OFF OFF OFF ON* OFF OFF ON* OFF ON* ON ON*FCH Hudson-M3L USB Port ListUSB1.1 Port0 Port1 USB2.0 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port10 Right USB NC NCBrazos PCIE Port ListPCIE0 APU PCIE1 PCIE2 PCIE3 PCIE0 FCH PCIE1 PCIE2 PCIE3 LAN WLAN NC NC GPU PCIE x4FCH Hudson-M3L SATA Port ListSATA0 SATA1 SATA2 SATA3 SATA4 SATA5 HDD ODD NC1+1.5V +0.75VS +1.0VS +1.1VS +1.8VS +3VALW +3V_LAN +3VS +5VALW +5VS +VSB +RTCVCC +1.1VALWNC NC NCRight USB Mini-PCIE USB Camera NC CardReader BT NC NC NC Left USB1 Left USB2 NC NCON ON(WOL)Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.2EC SM Bus1 addressDeviceSmart BatteryEC SM Bus2 addressHEX 15H DeviceEMC1412-2 (dGPU) EMC1403-2(DDR,WLAN) SB-TSIBOM StructureUMA@ : UMA only PX@ : DIS muxluss PX 4.0 Robson@ : Robson GPU GIGA@ : RTL05@ : RTL DIMM@ : DIMM select CMOS@ : USB camera BT@ : BT function ME@ : ME components X76@, H1G@, H512@, S1G@, S512@ 45@ : 45 Level HDMI@ : HDMI function non HDMI@ : HDMI function2AddressxbAddressxb xb xbHEX F8H 9AH 98HPort11 Port12 Port13SM Bus Controller 0DeviceAPU SIC/SID (FCH_SMB3) H_THERMTRIP# (FCH_ALERT#)(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)AddressHEX: VRAM3SM Bus Controller 1DeviceDDR DIMM1 (FCH_SMB0) DDR DIMM2 (FCH_SMB0) WLAN (FCH_SMB0)(FCH_SMB0)Addressxb xbHEX90 92AN@ : Apple + Nokia ear phone combo A@ : Apple ear phone PCB@ : PCB PN 14@ : 14& 15@ : 15& BBH@ : BBH nonBBH@@ : nonBBH@344Security Classification Issued Date Compal Secret DataDeciphered DateCompal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C DNotes ListSize B Date: Document NumberLA8681PTuesday, November 29, 2011ERev 1.0 3 of 48Sheet54321Power-Up/Down Sequence1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. 2. VDDR3 should ramp-up before or simultaneously with VDDC.DWithout BACO option :PXS_RST# : Low -& Reset dGPU ; High -&Normal operation PXS_PWREN : Low -& dGPU Power OFF ; High -& dGPU Power ONBACO option :PXS_RST# : High -&Normal operation (dGPU is not reset on BACO mode) PXS_PWREN : Low -& dGPU Power OFF ; High -& dGPU Power ON (always High) dGPU Power Pins PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18 DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and SPV10 Voltage 1.8V PX 3.0 OFF BACO Mode Max current ON 1679mAD3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. 4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up. 5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).)1.0V 1.0V 3.3V Same as VDDCOFF OFF OFF OFFON ON ON ON Same as PCIE_VDDC575mA 2A 190mA 70mAVDDR3(3.3VGS) PCIE_VDDC(1.0V)CNote: Do not drive any IOs before VDDR3 is ramped up.PCIE_VDDC VDDR3 , and A2VDD BIF_VDDC (current consumption = 55mA@1.0V, in BACO mode) BIF_VDDC=VGA_CORE When GPU enable BIF_VDDC=1.0V When BACO VDDR1 VDDC/VDDCIVDDR1(1.5VGS) VDDC/VDDCI(1.12V) VDD_CT(1.8V)1.5V 1.12VOFF OFFOFF OFF2.8A 12.9ACiGPUPERSTb REFCLKBPXS_RST#dGPUPE_ENBACO SwitchBIF_VDDC PXS_PWREN PX_modeStraps Reset Straps Valid Global ASIC Reset+3.3VALWMOS+3.3VGSB1+1.0VGS +1.5VSI4800+1.0V+1.5VGSRegulator2+1.8VGS +BRegulator3+VGA_CORE+1.8VT4+16clockSI480054PWRGOODAASecurity Classification Issued DateCompal Secret DataDeciphered DateCompal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2dGPU Block DiagramSize B Date: Document NumberLA8681PTuesday, November 29, 2011 Sheet1Rev 1.0 4 of 4854321AAAU6PCB@AAAU22E1200@BBBU22E1800@PCB 0R3 LA-8681P REV0 M/B+1.8VSEM1200GBB22GVEM1800GBB22GVU22BDP MISC&23& HDMI_TX2P &23& HDMI_TX2N R404 1D2 1K_ 1K_ 1K_ 300_ 300_ 510_ 1K_0402_5%APU_DBREQ# APU_SVC APU_SVD APU_RST# APU_PWRGD TEST_25_L TEST36R399 1 R400 1 R405 2 R401 2 R402 1 R403 1&23& HDMI_TX1P &23& HDMI_TX1N &23& HDMI_TX0P &23& HDMI_TX0N &23& HDMI_CLKP &23& HDMI_CLKNC508 1 HDMI@ 0.1U_K 2 C509 1 0.1U_K 2 HDMI@ C510 1 HDMI@ 0.1U_K 2 C511 1 0.1U_K 2 HDMI@ C512 1 HDMI@ 0.1U_K 2 C513 1 0.1U_K 2 HDMI@ C514 1 HDMI@ 0.1U_K 2 C515 1 0.1U_K 2 HDMI@ &22& LVDS_A2 &22& LVDS_A2# &22& LVDS_A1 &22& LVDS_A1# &22& LVDS_A0 &22& LVDS_A0# &22& LVDS_ACLK &22& LVDS_ACLK# &10& APU_CLK &10& APU_CLK# &10& APU_DISP_CLK &10& APU_DISP_CLK# &44& APU_SVC &44& APU_SVDA8 B8 B9 A9 D10 C10 A10 B10 B5 A5 D6 C6 A6 B6 D8 C8 V2 V1 D2 D1 J1 J2DISPLAYPORT 1HDMI_TX2P_C HDMI_TX2N_C HDMI_TX1P_C HDMI_TX1N_C HDMI_TX0P_C HDMI_TX0N_C HDMI_CLKP_C HDMI_CLKN_CTDP1_TXP0 TDP1_TXN0 TDP1_TXP1 TDP1_TXN1 TDP1_TXP2 TDP1_TXN2 TDP1_TXP3 TDP1_TXN3 LTDP0_TXP0 LTDP0_TXN0 LTDP0_TXP1 LTDP0_TXN1 LTDP0_TXP2 LTDP0_TXN2 LTDP0_TXP3 LTDP0_TXN3 CLKIN_H CLKIN_LDP_ZVSS DP_BLON DP_DIGON DP_VARY_BL TDP1_AUXP TDP1_AUXN TDP1_HPDH3 G2 H2 H1 B2 C2 C1 A3 B3 D3 C12 D13 A12 B12 A13 B13 E1 E2 F2 D4 D12 R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5DP_ZVSSR398 12 150_0402_1% APU_ENBKL &22& APU_ENVDD &22& APU_BLPWM &22& HDMI_CLK &23& HDMI_DATA &23& HDMI_DET &23&DDISPLAYPORT 0LTDP0_AUXP LTDP0_AUXN LTDP0_HPD DAC_RED DAC_REDB DAC_GREEN DAC_GREENB DAC_BLUE DAC_BLUEB DAC_HSYNC DAC_VSYNC DAC_SCL DAC_SDA DAC_ZVSSEDID_CLK EDID_DATA LTDP0_HPD R407 1 R408 1 R409 1 R406 1EDID_CLK &22& EDID_DATA &22& 2 100K_0402_5% DAC_RED &24& DAC_GRN &24& DAC_BLU &24& CRT_HSYNC &24& CRT_VSYNC &24& CRT_DDC_CLK &24& CRT_DDC_DATA &24&2 150_ 150_ 150_0402_1%+3VSR510 1 R511 1 R410 1 R411 12 4.7K_ 4.7K_ 1K_ 1K_0402_5%EDID_CLK EDID_DATA APU_PROCHOT# APU_ALERT#_RDISP_CLKIN_H DISP_CLKIN_L SVC SVD SIC SID RESET_L PWROK PROCHOT_L THERMTRIP_L ALERT_L TDI TDO TCK TMS TRST_L DBRDY DBREQ_LCLKVGA DACDAC_ZVSSR413 1 PAD T66 PAD T672 499_0402_1% AMD check list update CSERTO ECC&16,29,30& EC_SMB_CK2 &16,29,30& EC_SMB_DA2R809 1 R810 12 0_ 0_0402_5%EC_SMB_CK2_R EC_SMB_DA2_RP3 P4 T3 T4&10& APU_RST# &10,44& APU_PWRGD @ C02_50V8J 1 &10,30,37& H_PROCHOT# 2 R808 1 2 0_0402_5%APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# &44& APU_VDDNB_RUN_FB_H &44& APU_VDD0_RUN_FB_H T77PAD &44& APU_VDD0_RUN_FB_LN2 N1 P1 P2 M4 M3 M1 F4 G1 F3 F1 B4 W11 V5JTAGTESTAPU_PROCHOT# U1 APU_THERMTRIP# U2 APU_ALERT#_R T2VDDCR_NB_SENSE VDDCR_CPU_SENSE VDDIO_MEM_S_SENSE VSS_SENSE RSVD_1 RSVD_2 RSVD_3TEST4 TEST5 TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST25_H TEST25_L TEST28_H TEST28_L TEST31 TEST33_H TEST33_L TEST34_H TEST34_L TEST35 TEST36 TEST37TEST15R415 1 @ 2 1K_0402_5% PAD T69 PAD T95 TEST18 R416 1 2 1K_0402_5% TEST19 R417 1 2 1K_0402_5% TEST25_H R419 1 2 510_0402_1% TEST_25_L TEST28_H PAD T71 TEST28_L PAD T72 TEST31 PAD T73 TEST33_H C516 1 R420 1 2 0.1U_Z TEST33_L C517 1 R421 1 2 0.1U_Z Delete Test point for layout limitation
non HDMI@ TEST35 R422 1 2 1K_0402_5% TEST36 TEST37 R958 1 HDMI@ 2 1K_0402_5% PAD T76 +1.8VSPAD T68CTRL2 51_ 51_0402_1%HDMI function enable R958 mount disable R422 mountTEST38 DMAACTIVE_L K3 T1 R423 1 2 1K_0402_5% ALLOW_STOP# &10& +1.8VS+3VSS IC E SERIES EME450GBB22GVA 1.65G BGA1B2R424 10K_0402_5%21K_ E APU_THERMTRIP#2R425+1.8VS Q79 1 H_THERMTRIP# &12& +1.8VS JHDT1 1 1K_ 1 3 5 7 9 11 13 15 17 19 CAMD Debug check the connect need or notB+1.8VSB 3MMBT3904_NL_SOT23-3 1 R427 @ 2 0_0402_5% R8422 4 6 8 10 12 14 16 18 202 4 6 8 10 12 14 16 18 20APU_TCK APU_TMS APU_TDI APU_TDO APU_PWRGD APU_RST# APU_DBRDY APU_DBREQ# J108_PLLTST0 J108_PLLTST1R843 2 R844 2 R845 21 1K_ 1K_ 1K_0402_5%If FCH internal pull-up disabled, level-shifter could be deleted. Need BIOS to disable internal pull-up!!need to pop for HDT debug
@ R846 1 R847 2 @ R848 2 @ R849 2 @ 0_0402_5% APU_TRST#_R 2 1 10K_ 10K_ 10K_0402_5%3 5 7 9 11 13 15 17 191APU_TRST#R851 1 @ R852 1 @2 0_ 0_0402_5%TEST19 TEST18Please be noted about TEST_18 and TEST_19ASAMTE_ASP--B @need to pop for HDT debug ASecurity Classification Issued Date Compal Secret DataDeciphered DateTitleCompal Electronics, Inc.FT1 CTRL/DP/CRT LA8681PSheet1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date:Rev 1.0 5 of 48Wednesday, November 30, 2011ABCDEU22E DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 &8,9& DDR_A_BS0 &8,9& DDR_A_BS1 &8,9& DDR_A_BS2 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 &8,9& DDR_A_DQS0 &8,9& DDR_A_DQS#0 &8,9& DDR_A_DQS1 &8,9& DDR_A_DQS#1 &8,9& DDR_A_DQS2 &8,9& DDR_A_DQS#2 &8,9& DDR_A_DQS3 &8,9& DDR_A_DQS#3 &8,9& DDR_A_DQS4 &8,9& DDR_A_DQS#4 &8,9& DDR_A_DQS5 &8,9& DDR_A_DQS#5 &8,9& DDR_A_DQS6 &8,9& DDR_A_DQS#6 &8,9& DDR_A_DQS7 &8,9& DDR_A_DQS#7 &8& &8& &8& &8& &9& &9& &9& &9& DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3 DDR_RST# DDR_EVENT# DDR_CKE0 DDR_CKE14R17 H19 J17 H18 H17 G17 H15 G18 F19 E19 T19 F17 E18 W17 E16 G15 R18 T18 F16 D15 B19 D21 H22 P23 V23 AB20 AA16 A16 B16 B20 A20 E23 E22 J22 J23 R22 P22 W22 V22 AC20 AC21 AB16 AC16 M17 M16 M19 M18 N18 N19 L18 L17 L23 N17 F15 E15M_ADD0 M_ADD1 M_ADD2 M_ADD3 M_ADD4 M_ADD5 M_ADD6 M_ADD7 M_ADD8 M_ADD9 M_ADD10 M_ADD11 M_ADD12 M_ADD13 M_ADD14 M_ADD15 M_BANK0 M_BANK1 M_BANK2 M_DM0 M_DM1 M_DM2 M_DM3 M_DM4 M_DM5 M_DM6 M_DM7 M_DQS_H0 M_DQS_L0 M_DQS_H1 M_DQS_L1 M_DQS_H2 M_DQS_L2 M_DQS_H3 M_DQS_L3 M_DQS_H4 M_DQS_L4 M_DQS_H5 M_DQS_L5 M_DQS_H6 M_DQS_L6 M_DQS_H7 M_DQS_L7 M_CLK_H0 M_CLK_L0 M_CLK_H1 M_CLK_L1 M_CLK_H2 M_CLK_L2 M_CLK_H3 M_CLK_L3 M_RESET_L M_EVENT_L M_CKE0 M_CKE1M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7 M_DATA8 M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55 M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63 M_VREFB14 A15 A17 D18 A14 C14 C16 D16 C18 A19 B21 D20 A18 B18 A21 C20 C23 D23 F23 F22 C22 D22 F20 F21 H21 H23 K22 K21 G23 H20 K20 K23 N23 P21 T20 T23 M20 P20 R23 T22 V20 V21 Y23 Y22 T21 U23 W23 Y21 Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18 AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15 M23DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63DDR_A_D[0..63] DDR_A_MA[0..15] DDR_A_DM[0..7]DDR_A_D[0..63] DDR_A_MA[0..15] DDR_A_DM[0..7]&8,9& &8,9& &8,9&4P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3 P_ZVDD_10PCIE I/FDDR SYSTEM MEMORYU22A &15& PCIE_CRX_GTX_P0 &15& PCIE_CRX_GTX_N0 &15& PCIE_CRX_GTX_P1 &15& PCIE_CRX_GTX_N1 &15& PCIE_CRX_GTX_P2 &15& PCIE_CRX_GTX_N2 &15& PCIE_CRX_GTX_P3 &15& PCIE_CRX_GTX_N3 +1.05VS PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3AA6 Y6 AB4 AC4 AA1 AA2 Y4 Y3 Y14P_GPP_RXP0 P_GPP_RXN0P_GPP_TXP0 P_GPP_TXN0 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3 P_ZVSSAB6 PCIE_CTX_C_GRX_P0 C518 1 AC6 PCIE_CTX_C_GRX_N0 C519 1 AB3 PCIE_CTX_C_GRX_P1 C520 1 AC3 PCIE_CTX_C_GRX_N1 C521 1 Y1 Y2 V3 V4PCIE_CTX_C_GRX_P2 C522 1 PCIE_CTX_C_GRX_N2 C523 1 PCIE_CTX_C_GRX_P3 C524 1 PCIE_CTX_C_GRX_N3 C525 1 R436 12 0.1U_K 2 0.1U_K 2 0.1U_K 2 0.1U_K 2 0.1U_K 2 0.1U_K 2 0.1U_K 2 0.1U_K 21.27K_0402_1%PCIE_CTX_GRX_P0 &15& PCIE_CTX_GRX_N0 &15& PCIE_CTX_GRX_P1 &15& PCIE_CTX_GRX_N1 &15& PCIE_CTX_GRX_P2 &15& PCIE_CTX_GRX_N2 &15& PCIE_CTX_GRX_P3 &15& PCIE_CTX_GRX_N3 &15&331 2 R435 2K_0402_1%P_ZVDD_10AA14 P_ZVSSLess than 1& Less than 1&&10& UMI_RX0P &10& UMI_RX0N &10& UMI_RX1P &10& UMI_RX1N &10& UMI_RX2P &10& UMI_RX2N &10& UMI_RX3P &10& UMI_RX3NAA12 Y12 AA10 Y10 AB10 AC10 AC7 AB7P_UMI_RXP0 P_UMI_RXN0P_UMI_TXP0 P_UMI_TXN0AB12 AC12 AC11 AB11 AA8 Y8 AB8 AC8UMI_TX0P_C UMI_TX0N_C UMI_TX1P_C UMI_TX1N_C UMI_TX2P_C UMI_TX2N_C UMI_TX3P_C UMI_TX3N_CC526 1 C527 1 C528 1 C529 1 C530 1 C531 1 C532 1 C533 12 2 2 2 2 2 2 20.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_KUMI_TX0P &10& UMI_TX0N &10& UMI_TX1P &10& UMI_TX1N &10& UMI_TX2P &10& UMI_TX2N &10& UMI_TX3P &10& UMI_TX3N &10&P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3UMI I/FP_UMI_RXP1 P_UMI_RXN1P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3&8,9& DDR_RST# &8,9& DDR_EVENT# &8,9& DDR_CKE0 &8,9& DDR_CKE1S IC E SERIES EME450GBB22GVA 1.65G BGA&8& &8& &9& &9& &8& &8& &9& &9&DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#W19 V15 U19 W15 T17 W16 U17 V16 U18 V19 V17M0_ODT0 M0_ODT1 M1_ODT0 M1_ODT1 M0_CS_L0 M0_CS_L1 M1_CS_L0 M1_CS_L12DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB#2+MEM_VREF&8,9& DDR_A_RAS# &8,9& DDR_A_CAS# &8,9& DDR_A_WE#M_RAS_L M_CAS_L M_WE_L M_ZVDDIO_MEM_S S IC E SERIES EME450GBB22GVA 1.65G BGAR437 2 M22 M_ZVDDIO_MEM_S1+1.5V_APU39.2_0402_1%+1.5V_APU+1.5V_APUR438 1K_0402_1%1R444 12 1K_0402_5%DDR_EVENT#2+MEM_VREF21R439 1K_0402_1%1C534C5351112_50V7K20.1U_ZPlace within 1000 mils to APU Security Classification Issued Date Compal Secret DataDeciphered DateTitleCompal Electronics, Inc.FT1 DDRIII/UMI/PCIE LA8681PSheet 6 of 48ETHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C DSize Document Number Custom Date:Rev 1.0Wednesday, November 30, 201154321+1.8VS +APU_CORE +APU_CORED11AE5 E6 F5 F7 G6 G8 H5 H7 J6 J8 L7 M6 M8 N7 R8U22C TSense/PLL/DP/PCIE/IO VDDCR_CPU_1 VDDCR_CPU_2 VDDCR_CPU_3 VDDCR_CPU_4 VDDCR_CPU_5 VDDCR_CPU_6 VDDCR_CPU_7 VDDCR_CPU_8 VDDCR_CPU_9 VDDCR_CPU_10 VDDCR_CPU_11 VDDCR_CPU_12 VDDCR_CPU_13 VDDCR_CPU_14 VDDCR_CPU_15 VDDCR_NB_1 VDDCR_NB_2 VDDCR_NB_3 VDDCR_NB_4 VDDCR_NB_5 VDDCR_NB_6 VDDCR_NB_7 VDDCR_NB_8 VDDCR_NB_9 VDDCR_NB_10 VDDCR_NB_11 VDDCR_NB_12 VDDCR_NB_13 VDDCR_NB_14 VDDCR_NB_15 VDDCR_NB_16 VDDCR_NB_17 VDDCR_NB_18 VDDCR_NB_19 VDDCR_NB_20 VDDCR_NB_21 VDDCR_NB_22 VDDIO_MEM_S_1 VDDIO_MEM_S_2 VDDIO_MEM_S_3 VDDIO_MEM_S_4 VDDIO_MEM_S_5 VDDIO_MEM_S_6 VDDIO_MEM_S_7 VDDIO_MEM_S_8 VDDIO_MEM_S_9 VDDIO_MEM_S_10 VDDIO_MEM_S_11 VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6 VDD_18_7 U8 W8 U6 U9 W6 T7 V72A+VDD_18 10U_V6M 1U_V6K C538 1U_V6K C547 1U_V6K C548 180P_J C537 0.1U_K C546 1U_V6K C549 C545 1 1 1 1 1 1 1L29 2 1 FBMA-L11-LMA30T_0805 Change from SM to SD100816U22D A7 B7 B11 B17 B22 C4 D5 D7 D9 D11 D14 B15 D17 D19 E7 E9 E12 E20 F8 F11 F13 G4 G5 G7 G9 G12 G20 G22 H6 H11 H13 J4 J5 J7 J20 K10 K14 L4 L6 L8 L11 L13 L20 L22 M7 N4 N6 N8 N11 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSSBG_DAC N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11D2222222CPU CORE1U_V6K1U_V6K1U_V6K1U_V6K180P_J180P_JC550C551C552C553C554C555111111Change from SM to SD.8VSGND222222+APU_CORE_NB0.15AL30 10U_V6M 180P_J C557 VDD_18_DAC W9 +VDD_18_DAC 1U_V6K C558 C556 1 1 1 2 1 FBMA-L11-LMA30T_0805 DAC10AE8 E11 E13 F9 F12 G11 G13 H9 H12 K11 K13 L10 L12 L14 M11 M12 M13 N10 N12 N14 P11 P13POWER0.2ADIS PLL U11 +VDDL_10+1.0VS has been raised to +1.05VS for AMD design guide 4 update +1.05VSGPU AND NB CORE2220.1U_K0.1U_K0.1U_K0.1U_KC559C560C561C562C563111110.1U_KL31 1U_V6K C567 10U_V6M 180P_J C565 0.1U_K C566 VDDPL_10 2 1 1 1 1 1 FBMA-L11-LMA30T_080522222place C564 2 close APU ball 5.5A+VDD_10 VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4 U13 W13 V12 T12 1 PCIE/IO/DDR3 PhyC564222L32 2 10U_V6M C574 10U_V6M 1 FBMA-L11-LMA30T_0805 Change from SM to SDU_V6K C573180P_J C5690.1U_K C570CC1102+1.5V_APU2AG16 G19 E17 J16 L16 L19 N16 R16 R19 W18 U16110.1U_K C57111U_V6K C572+APU_CORE_NB111C2222222DDR31U_V6K1U_V6K1U_V6K1U_V6K1U_V6K180P_JC582C583C584C585C586C587C5881111111180P_JDP Phy/IO0.5A0.1U_K C581 1U_V6K VDD_33 A4 C580 1 1+3VS S IC E SERIES EME450GBB22GVA 1.65G BGA2222222S IC E SERIES EME450GBB22GVA 1.65G BGA220.1U_K0.1U_K0.1U_K0.1U_KC591C592C59310U_V6MC5892C5901121U_V6K1U_V6K10U_V6M222C5941111+1.5V_APU21U_V6KC595C596C597BC59811111U_V6KB2222+1.5V_APU 180P_J 180P_J 0.1U_K 0.1U_K 0.1U_K 1 1 1 1 1+1.5VC599C600C601C602C603@ 1 1J15 2 222222JUMP_43X79By case (Along split)+1.5V_APU+1.5V_APUPOWER180P_J 180P_J 180P_J C608 C609 C610 C611 C612 C613 C614 C615 1 1 1 1 1 1 1 180P_J 0.1U_K 0.1U_K 0.1U_K 0.1U_K 1AA22U_V6M1 C622 + 2 @330U_2.5V_M@C6231222222222Near CPU SocketSecurity ClassificationCompal Secret DataDeciphered DateIssued DateTitle Size C Date:Compal Electronics, Inc.P07-FT1 PWR/VSSDocument NumberTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2LA8681PTuesday, November 29, 20111Rev 1.0 Sheet 7 of 4854321+1.5V JDIMM1 +VREF_DQ _50V7K 0.1U_Z 1 1 DDR_A_D0 DDR_A_D1 DDR_A_DM0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT GND1 BOSS1 ME@ VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT GND2 BOSS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208+1.5VDDR_A_D4 DDR_A_D5 DDR_A_DQS#0 &6,9& DDR_A_DQS0 &6,9& DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR_A_DM1 DDR_RST# &6,9& DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 &6,9& DDR_A_DQS3 &6,9& DDR_A_D30 DDR_A_D31+1.5V DDR_A_D[0..63] DDR_A_MA[0..15] DDR_A_DM[0..7] DDR_A_D[0..63] &6,9& 2 R440 1K_+1.5V 2 R441 1K_ +VREF_CAC626C627DDR_A_MA[0..15] &6,9& DDR_A_DM[0..7] &6,9& +VREF_DQ 222DD&6,9& DDR_A_DQS#1 &6,9& DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 &6,9& DDR_A_DQS#2 &6,9& DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27R442 1K_ 12 R443 1K_0402_1%Combine to one?&6,9& DDR_CKE0CDDR_CKE1 &6,9& DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 &6& DDR_A_CLK#1 &6& DDR_A_BS1 &6,9& DDR_A_RAS# &6,9& DDR_CS0_DIMMA# &6& DDR_A_ODT0 &6& DDR_A_ODT1 &6&+1.5V 0.1U_Z 2 C628 1 0.1U_Z 1 C629 0.1U_Z 2 C630 1 C631 0.1U_Z 2 C632 1 C633C&6,9& DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 &6& DDR_A_CLK0 &6& DDR_A_CLK#0 DDR_A_MA10 &6,9& DDR_A_BS0 &6,9& DDR_A_WE# &6,9& DDR_A_CAS# DDR_A_MA13 &6& DDR_CS1_DIMMA#2221 0.1U_Z1 0.1U_ZCRB 0.1u X1+0.75VS +VREF_CA4.7u X1CRB100U+1.5VX2_50V7KC645C642C644C643B&6,9& DDR_A_DQS#4 &6,9& DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 &6,9& DDR_A_DQS#6 &6,9& DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 R445 10K_ 2DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D451C64110.1U_Z121 + 2220U_6.3V_MDDR_A_D32 DDR_A_D33DDR_A_D36 DDR_A_D374.7U_V6K0.1U_ZB2212 DDR_A_DQS#5 &6,9& DDR_A_DQS5 &6,9&DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 &6,9& DDR_A_DQS7 &6,9& DDR_A_D62 DDR_A_D63 DDR_EVENT# &6,9& FCH_SMDAT0 &9,12,29& FCH_SMCLK0 &9,12,29& +0.75VSPlace near JDIMM1SFAA+3VS C646 12.2U_V4ZC64710.1U_Z1 R446 10K_22Security ClassificationCompal Secret DataDeciphered DateLCN_DAN06-KDDR3 SO-DIMM A Reverse TypeIssued DateTitleCompal Electronics, Inc.DDR3 SODIMM-I Socket LA8681PSheet 8 of 481THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2Size Document Number Custom Date:Rev 1.0Wednesday, November 30, 20115454321+1.5V JDIMM2 +VREF_DQ _50V7K 0.1U_Z 1 1 DDR_A_D0 DDR_A_D1 DDR_A_DM0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 ME@ VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72+1.5VDDR_A_D4 DDR_A_D5 DDR_A_DQS#0 &6,8& DDR_A_DQS0 &6,8& DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR_A_DM1 DDR_RST# &6,8& DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 &6,8& DDR_A_DQS3 &6,8& DDR_A_D30 DDR_A_D31 2 DDR_A_D[0..63] DDR_A_MA[0..15] DDR_A_DM[0..7]DIMM@DDIMM@ C648 C649DDR_A_D[0..63]&6,8&D22DDR_A_MA[0..15] &6,8& DDR_A_DM[0..7] &6,8&&6,8& DDR_A_DQS#1 &6,8& DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 &6,8& DDR_A_DQS#2 &6,8& DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27+1.5V 0.1U_Z 2 C651 DIMM@ 1 0.1U_Z 2 2 0.1U_Z 2 C655 DIMM@ 1C2C&6,8& DDR_CKE0 &6,8& DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 &6& DDR_B_CLK2 &6& DDR_B_CLK#2 DDR_A_MA10 &6,8& DDR_A_BS0 &6,8& DDR_A_WE# &6,8& DDR_A_CAS# DDR_A_MA13 &6& DDR_CS1_DIMMB#DDR_A_D32 DDR_A_D33 &6,8& DDR_A_DQS#4 &6,8& DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 &6,8& DDR_A_DQS#6 &6,8& DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 For DRAM strap pin reservation
DDR_A_D58 DDR_A_D59 DIMM@ R961 1 2 10K_0402_5% +3VSABC667 2.2U_V4Z DIMM@1173 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205DIMM@CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 G1CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G274 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206DDR_CKE1 &6,8& DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0C650 DIMM@ 1 0.1U_ZC652 C653 C654 DIMM@ DIMM@ DIMM@ 1 1 1 0.1U_Z 0.1U_ZCRB 0.1u X1+0.75VS 4.7U_V6K 0.1U_Z DDR_B_CLK3 &6& DDR_B_CLK#3 &6& C664 DDR_A_BS1 &6,8& DDR_A_RAS# &6,8& DDR_CS0_DIMMB# &6& DDR_B_ODT0 &6& DDR_B_ODT1 &6& +VREF_CA4,7uX112 C6632 DIMM@1DIMM@DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DIMM@_50V7K0.1U_ZPlace near JDIMM21 C666 DIMM@B1 C66522DDR_A_DQS#5 &6,8& DDR_A_DQS5 &6,8& DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 &6,8& DDR_A_DQS7 &6,8& DDR_A_D62 DDR_A_D63 DDR_EVENT# &6,8& FCH_SMDAT0 &8,12,29& FCH_SMCLK0 &8,12,29& +0.75VSA2C668 2 0.1U_ZCRBonly one 4.7kDIMM@ R962 10K_0402_5%2LCN_DAN06-KDDR3 SO-DIMM B Reverse TypeSecurity Classification Issued Date Compal Secret DataDeciphered Date1TitleCompal Electronics, Inc.DDR3 SODIMM-II Socket LA8681PSheet1For DRAM strap pin reservation THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.4 3 2Size Document Number Custom Date:Rev 1.0 9 of 48Wednesday, November 30, 20115ABCDEC146 place close to FCHC146 12 150P_J APU_PCIE_RST#_C 2 33_0402_5% A_RST# UMI_RXP0_C UMI_RXN0_C UMI_RXP1_C UMI_RXN1_C UMI_RXP2_C UMI_RXN2_C UMI_RXP3_C UMI_RXN3_C AE2 AD5 AE30 AE32 AD33 AD31 AD28 AD29 AC30 AC32 AB33 AB31 AB28 AB29 Y33 Y31 Y28 Y29 R94 R88 1 1 1 1 1 1 2 2 2 2 2 590_ 2K_.1U_K 0.1U_K 0.1U_K 0.1U_K PCIE_CALRP PCIE_CALRN PCIE_FTX_DRX_P0 PCIE_FTX_DRX_N0 PCIE_FTX_DRX_P1 PCIE_FTX_DRX_N1 AF29 AF31 V33 V31 W30 W32 AB26 AB27 AA24 AA23 AA27 AA26 W27 V27 V26 W26 W24 W23U2A HUDSON-2 PCI CLKSPLT_RST# &6& &6& &6& &6& &6& &6& &6& &6& &6& &6& &6& &6& &6& &6& &6& &6& UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N C147 C148 C149 C150 C151 C152 C153 C154 1 1 1 1 1 1 1 11 R557 2 2 2 2 2 2 2 2PCIE_RST# A_RST# UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N PCIE_CALRP PCIE_CALRN GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_KPCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38 PCICLK4/14M_OSC/GPO39 PCIRST# AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1#/GPIO40 REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42 GNT0# GNT1#/GPO44 GNT2#/SD_LED/GPO45 GNT3#/CLK_REQ7#/GPIO46 CLKRUN# LOCK# INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35AF3 AF1 AF5 AG2 AF6 AB5PCI_CLK1 &14& PCI_CLK3 &14& PCI_CLK4 &14&+3VALW AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9 AF18 AE18 AC16 AD181APU_PCIE_RST #: Reset PCIE device on APUMC74VHC1G08DFT2G SC70 5P @ R692 2 B 1 2 33_ A 1 1 @ R693 8.2K_ @ 5C789 @ 1 2 0.1U_Z1PCI EXPRESS INTERFACESAPU_PCIE_RST#_CPY G 34 2 U43APU_PCIE_RST# &15,29&@ C790 150P_JR866 0_+VDDAN_11_PCIE2LAN WLAN&25& &25& &29& &29&PCIE_FTX_C_DRX_P0 PCIE_FTX_C_DRX_N0 PCIE_FTX_C_DRX_P1 PCIE_FTX_C_DRX_N1C718 C720 C721 C719@R695 @ R695 1 2 0_0402_5%PLT_RST# &25,30&R692/ C790 close to FCH2PCI INTERFACE&25& &25& &29& &29&PCIE_FRX_DTX_P0 PCIE_FRX_DTX_N0 PCIE_FRX_DTX_P1 PCIE_FRX_DTX_N1PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27&14& &14& &14& &14& &14&2+1.1VS_CKVDDR9512 2K_0402_1%CLK_CALRNF27CLK_CALRNG30 G28 &5& APU_DISP_CLK &5& APU_DISP_CLK# R26 T26 H33 H31 &5& APU_CLK &5& APU_CLK# T24 T23 J30 K29 H27 H28 J27 K26PCIE_RCLKP PCIE_RCLKN DISP_CLKP DISP_CLKN DISP2_CLKP DISP2_CLKN APU_CLKP APU_CLKN SLT_GFX_CLKP SLT_GFX_CLKN GPP_CLK0P GPP_CLK0N GPP_CLK1P GPP_CLK1N CLOCK GENERATOR GPP_CLK2P GPP_CLK2N GPP_CLK3P GPP_CLK3N GPP_CLK4P GPP_CLK4N GPP_CLK5P GPP_CLK5N GPP_CLK6P GPP_CLK6N GPP_CLK7P GPP_CLK7N GPP_CLK8P GPP_CLK8N 14M_25M_48M_OSCModule design have reserve GPIO44,45 for VGA power enable and resetT14VGA&15& CLK_PCIE_VGA &15& CLK_PCIE_VGA#R98 R991 12 0_ 0_0402_5%CLK_PCIE_VGA_R CLK_PCIE_VGA#_RT99WLAN LAN3&29& CLK_PCIE_WLAN &29& CLK_PCIE_WLAN# &25& CLK_PCIE_LAN &25& CLK_PCIE_LAN#R102 1 R103 1 R100 1 R101 12 0_ 0_ 0_ 0_0402_5%CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R CLK_PCIE_LAN_R CLK_PCIE_LAN#_RF33 F31 E33 E31 M23 M24 M27 M26 N25 N26 R23 R24 N27 R27LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/CLK_REQ6#/GPIO49 SERIRQ/GPIO48B25 D25 D27 C28 A26 A29 A31 B27 AE27 AE19R558 12 22_0402_5%LPCLPC_CLK1 &14& LPC_AD0 &29,30& LPC_AD1 &29,30& LPC_AD2 &29,30& LPC_AD3 &29,30& LPC_FRAME# &29,30& SERIRQ &30&CLK_PCI_EC &14,30& @ 1 2 R670 0_0402_5%CLK_PCI_DB &29&3T101@ 22_0402_5% R559 1 2APUDMA_ACTIVE# PROCHOT# APU_PG LDT_STP# APU_RST# S5_CORE_EN RTCCLK INTRUDER_ALERT# VDDBT_RTC_GG25 E28 APU_PROCHOT#_R E26 G26 F26 H7 F1 F3 E6 G2 32K_X1R151@2 0_0402_5%ALLOW_STOP# &5& H_PROCHOT# &5,30,37&APU_PWRGD &5,44& APU_RST# &5&J26T100 RTC_CLK &14,30&change to 510 OhmW=20mils1U_V6K 1 C156 2 2 1 R105 +RTCBATT 2 510_ CLRP1 @ SHORT PADS25M_X1C3125M_X1 S5 PLUS32K_X125M_X2C3325M_X232K_X2 25M_X1 S IC 218- HUDSON-M3L FCBGA 656P C38 25M_X24G432K_X21 2 R106 1M_ 2 OSC NC NC OSC 4 1C158 12 132K_X122P_J R107 20M_0402_5%for Clear CMOS2 Y1 32.768KHZ_12.5PF_CMDZFT 2 1 32K_X24Y4 1 25MHZ_20PF_FSX3M-25.M20FDO 1 C157 22P_J C155 22P_JC159 12Security Classification Issued Date Compal Secret DataDeciphered Date2222P_JTitleCompal Electronics, Inc.FCH PCIE/CLK/PCI/LPC/RTC LA8681PSheetETHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C DSize Document Number Custom Date:Rev 0.1 10 of 48Wednesday, November 30, 2011ABC4MB SPI ROM & Non-share ROM.DESPI_CLK_FCH+3VALW R111 33_0402_5% @ U2B1HUDSON-2R108 1 SD_CLK/SCLK_2/GPIO73 SD_CMD/SLOAD_2/GPIO74 SD_CD/GPIO75 SD_WP/GPIO76 SD_DATA0/SDATI_2/GPIO77 SD_DATA1/SDATO_2/GPIO78 SD_DATA2/GPIO79 SD_DATA3/GPIO80 GBE_COL GBE_CRS GBE_MDCK GBE_MDIO GBE_RXCLK GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0 GBE_RXCTL/RXDV GBE_RXERR GBE_TXCLK GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0 GBE_TXCTL/TXEN GBE_PHY_PD GBE_PHY_RST# GBE_PHY_INTR SPI_DI/GPIO164 SPI_DO/GPIO163 SPI_CLK/GPIO162 SPI_CS1#/GPIO165 ROM_RST#/SPI_WP#/GPIO161 VGA_RED AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14 AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9 V6 V5 V3 T6 V1 L30 L32 M29 M28 N30 M33 N32 K31 V28 V29 U28 T31 T33 T29 T28 R32 R30 P29 P28 C29 N2 M3 L2 N4 P1 P3 M1 M5 AG16 AH10 A28 G27 L4 1 R148 2 10K_ R137 1 R138 1 R139 2 10K_ 10K_ 10K_0402_5%10K_ SPI_HOLD#+3VALW 0.1U_Z C165 1 2HDD&28& SATA_FTX_C_DRX_P0 &28& SATA_FTX_C_DRX_N0 &28& SATA_FRX_C_DTX_N0 &28& SATA_FRX_C_DTX_P0 &28& SATA_FTX_C_DRX_P1 &28& SATA_FTX_C_DRX_N1 &28& SATA_FRX_C_DTX_N1 &28& SATA_FRX_C_DTX_P1AK19 AM19 AL20 AN20 AN22 AL22 AH20 AJ20 AJ22 AH22 AM23 AK23SATA_TX0P SATA_TX0N SATA_RX0N SATA_RX0P SATA_TX1P SATA_TX1N SATA_RX1N SATA_RX1P SATA_TX2P SATA_TX2N SATA_RX2N SATA_RX2P SATA_TX3P SATA_TX3N SATA_RX3N SATA_RX3P SATA_TX4P SATA_TX4N SATA_RX4N SATA_RX4P SATA_TX5P SATA_TX5N SATA_RX5N SATA_RX5P NC6 NC7 NC8 NC9 GBE LANC160 22P_J @2R112 12 SPI_WP#_R 3.3K_0402_5%11SD CARDR115 0_0402_5% SPI_SB_CS0#_R 1 2 SPI_SO_R 1 2ODDSPI_WP#U4 SPI_SB_CS0# 1 CS# VCC 8 SPI_SO_L 2 7 HOLD# SPI_WP#_R 3 SO/SIO1 WP# SCLK 6 33_ GND 5 SI/SIO0 R117 W25Q32BVSSIG SOIC 8 R116 0_ 2R110 SPI_HOLD# 0_0402_5% SPI_CLK_FCH 1 2 SPI_SI 1 2SPI_CLK_FCH_R SPI_SI_R33_0402_5% R119 R110 place close to FCH +3VALWGBE_PHY_INTRR121 12 10K_0402_5%FCH-M3L NC pin2AH24 AJ24 AN24 AL24 AL26 AN26 AJ26 AH26 AN29 AL28 AK27 AM27 AL29 AN31 AL31 AL33 AH33 AH31 AJ33 AJ31SERIAL ATAGBE_PHY_INTR SPI_SO_R SPI_SI_R SPI_CLK_FCH_R SPI_SB_CS0#_R SPI_WP#2SPI ROMVGA_GREEN NC10 NC11 VGA_BLUE VGA DAC NC12 NC13 VGA_HSYNC/GPO68 VGA_VSYNC/GPO69 VGA_DDC_SDA/GPO70 VGA_DDC_SCL/GPO71 VGA_DAC_RSETFCH-M3L NC pin1K_0402_1% +AVDD_SATA +3VS 931_0402_1%2 2 @1 R128 1 R130 2 R133SATA_CALRP SATA_CALRNAF28 AF27 AD22 AF21SATA_CALRP SATA_CALRN SATA_ACT#/GPIO67 SATA_X1 VGA MAINLINK10K_AUX_VGA_CH_P AUX_VGA_CH_N AUXCAL ML_VGA_L0P ML_VGA_L0N ML_VGA_L1P ML_VGA_L1N ML_VGA_L2P ML_VGA_L2N ML_VGA_L3P ML_VGA_L3N ML_VGA_HPD/GPIO22933AG21SATA_X2T48 &28& BT_ON# &29& BT_DISABLE# &29& WL_OFF#AH16 AM15 AJ16 AK15 AN16 AL16 K6FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54 FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58 TEMPIN0/GPIO171VIN0/GPIO175 HW MONITOR VIN1/GPIO176 VIN2/SDATI_1/GPIO177 VIN3/SDATO_1/GPIO178 VIN4/SLOAD_1/GPIO179 VIN5/SCLK_1/GPIO180&28& ODD_EN 1 R146 1 R149 1 R151 2 10K_ 10K_ 10K_0402_5%K5 K3 M6TEMPIN1/GPIO172 TEMPIN2/GPIO173 TEMPIN3/TALERT#/GPIO174VIN6/GBE_STAT3/GPIO181 VIN7/GBE_LED3/GPIO182 NC1 NC2 NC3 NC4 NC54Need to enable internal pull down to leave unconnected4S IC 218- HUDSON-M3L FCBGA 656P C38Security Classification Issued Date Compal Secret DataDeciphered DateCompal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C DFCH SATA/SPI/VGA/HWM/SDSize Document Number Custom Date:LA8681PSheetERev 0.1 11 of 48Wednesday, November 30, 2011ABCDEPCIE_RST2 : Reset PCIE device on Hudson 3T17 &30& EC_LID_OUT# &30& PM_SLP_S3# &30& PM_SLP_S5# &30& PBTN_OUT# &30,44& FCH_PWRGD AB6 R2 W7 T3 W2 J4 N7 T9 T10 V9 AE22 AG19 R9 C26 T5 U4 K1 V7 R10 AF19 U2 AG24 AE24 AE26 AF22 AH17 AG18 AF24 AD26 AD25 T7 R7 AG25 AG22 J2 AG26 V8 W8 Y6 V10 AA8 AF25 M7 R8 T1 P6 F5 P5 J7 T8U2D HUDSON-2 PCIE_RST2#/PCI_PME#/GEVENT4# RI#/GEVENT22# SPI_CS3#/GBE_STAT1/GEVENT21# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD TEST0 TEST1/TMS TEST2 GA20IN/GEVENT0# KBRST#/GEVENT1# LPC_PME#/GEVENT3# LPC_SMI#/GEVENT23# LPC_PD#/GEVENT5# SYS_RESET#/GEVENT19# WAKE#/GEVENT8# IR_RX1/GEVENT20# THRMTRIP#/SMBALERT#/GEVENT2# WD_PWRGD RSMRST# CLK_REQ4#/SATA_IS0#/GPIO64 CLK_REQ3#/SATA_IS1#/GPIO63 SMARTVOLT1/SATA_IS2#/GPIO50 CLK_REQ0#/SATA_IS3#/GPIO60 SATA_IS4#/FANOUT3/GPIO55 SATA_IS5#/FANIN3/GPIO59 SPKR/GPIO66 SCL0/GPIO43 SDA0/GPIO47 SCL1/GPIO227 SDA1/GPIO228 CLK_REQ2#/FANIN4/GPIO62 CLK_REQ1#/FANOUT4/GPIO61 IR_LED#/LLB#/GPIO184 SMARTVOLT2/SHUTDOWN#/GPIO51 DDR3_RST#/GEVENT7#/VGA_PD GBE_LED0/GPIO183 SPI_HOLD#/GBE_LED1/GEVENT9# GBE_LED2/GEVENT10# GBE_STAT0/GEVENT11# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# BLINK/USB_OC7#/GEVENT18# USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GEVENT17# USB_OC4#/IR_RX0/GEVENT16# USB_OC3#/AC_PRES/TDO/GEVENT15# USB_OC2#/TCK/GEVENT14# USB_OC1#/TDI/GEVENT13# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_HSD8P USB_HSD8N USB_HSD7P USB_HSD7N USB_HSD6P USB_HSD6N USB_HSD5P USB_HSD5N USB_HSD4P USB_HSD4N USB_HSD3P USB_HSD3N USB_HSD2P USB_HSD2N USB_HSD1P USB_HSD1N USB_HSD0P USB_HSD0N USBSS_CALRP USBSS_CALRN USB_SS_TX3P USB_SS_TX3N USB_SS_RX3P USB_SS_RX3N ACPI / WAKE UP EVENTS USB MISC USBCLK/14M_25M_48M_OSC USB_RCOMP USB_FSD1P/GPIO186 USB_FSD1N USB 1.1 USB_FSD0P/GPIO185 USB_FSD0N USB_HSD13P USB_HSD13N USB_HSD12P USB_HSD12N USB_HSD11P USB_HSD11N USB_HSD10P USB_HSD10N USB_HSD9P USB_HSD9N G8 B9 H1 H3 H6 H5 H10 G10 K10 J12 G12 F12 K12 K13 B11 D11 E10 F10 C10 A10 H9 G9 A8 C8 F8 E8 C6 A6 C5 A5 C1 C3 E1 E3 C16 A16 A14 C14 C12 A12 D15 B15 E14 F14 F15 G15 H13 G13 J16 H16 J15 K15 H19 G19 G22 G21 E22 H22 J22 H21 K21 K22 F22 F24 E24 B23 C24 F18 USB30_FTX_DRX_P1 USB30_FTX_DRX_N1 USB30_FRX_DTX_P1 USB30_FRX_DTX_N1 USB30_FTX_DRX_P0 USB30_FTX_DRX_N0 USB30_FRX_DTX_P0 USB30_FRX_DTX_N0 R165 R167 R227 R228 10K_K_K_K_0402_5% USB30_FTX_DRX_P1 &34& USB30_FTX_DRX_N1 &34& USB30_FRX_DTX_P1 &34& USB30_FRX_DTX_N1 &34& USB30_FTX_DRX_P0 &34& USB30_FTX_DRX_N0 &34& USB30_FRX_DTX_P0 &34& USB30_FRX_DTX_N0 &34& USBSS_CALRP USBSS_CALRN USB20_P6 &28& USB20_N6 &28& USB30_P11 &34& USB30_N11 &34& USB_RCOMP R154 1 2 11.8K_0402_1%FCH_PWRGD TEST0 TEST1 TEST2FCH-M3L NC pin11&30& GATEA20 &30& KBRST# &30& EC_SCI# &30& EC_SMI# +3VALW R155 1 @ 2 10K_0402_5% SYS_RESET# &25,29& FCH_PCIE_WAKE# &5& H_THERMTRIP# &30& EC_RSMRST# &25& LAN_CLKREQ# WD_PWRGDFCH-M3L NC pin FCH-M3L NC pinUSB20_P3 &22& USB20_N3 &22& USB20_P2 &29& USB20_N2 &29& USB20_P1 &32& USB20_N1 &32& USB20_P0 &33& USB20_N0 &33& R864 1 R865 1 2 1K_ 1K_0402_1% USB20_P5 &32& USB20_N5 &32&USB30_P10 &34& USB30_N10 &34&LP2 LP1RootUSB 2.0Root BT CR CMOS WLAN Root RP2 RP1+FCH_VDD_11_SSUSB_S+3VALWFor FCH internal debug use@ @ @ 2 2.2K_ 2.2K_ 2.2K_0402_5% TEST0 TEST1 TEST2&27& FCH_SPKR &8,9,29& FCH_SMCLK0 &8,9,29& FCH_SMDAT0 &29& WLAN_CLKREQ# &15,17,43& VGA_PWRGDR179 1 R181 1 R183 12FCH_SMCLK0 FCH_SMDAT0 FCH_SMCLK1 FCH_SMDATA1GPIO2&16& PEG_CLKREQ#R156 2@1 0_0402_5% PEG_CLKREQ#_R USB_OC7#&28& ODD_DETECT# R883 R624 R625 R174 R618 R649 R620 R163 R164 R16931 1 1 1 1 1 1 1 1 1 1@2 10K_ 10K_ 10K_ 10K_0402_5%USB_OC7# USB_OC2# USB_OC1# USB_OC0# ODD_DA#_FCH ODD_DETECT# USB_OC5# USB_OC3# H_THERMTRIP# EC_LID_OUT# &27& HDA_BITCLK_AUDIO &27& HDA_SDOUT_AUDIO &27& HDA_SDIN0&32& USB_OC2# &33& USB_OC1# &34& USB_OC0#USB_OC3# USB_OC2# USB_OC1# USB_OC0#USB OC+3VALW&28& ODD_DA#_FCHUSB_OC5#@ @ @ @ @ @ @2 10K_ 10K_ 10K_ 10K_ 10K_ 100K_0402_5%R159 1 R160 12 33_ 33_0402_5%HD AUDIOHDA_BITCLK HDA_SDOUT HDA_SDIN0&27& HDA_SYNC_AUDIO &27& HDA_RST_AUDIO#R161 1 R162 12 33_ 33_0402_5%HDA_SYNC HDA_RST#AB3 AB1 AA2 Y5 Y3 Y1 AD6 AE4AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 AZ_SDIN1/GPIO168 AZ_SDIN2/GPIO169 AZ_SDIN3/GPIO170 AZ_SYNC AZ_RST#USB_SS_TX2P USB_SS_TX2N USB 3.0 USB_SS_RX2P USB_SS_RX2N USB_SS_TX1P USB_SS_TX1N USB_SS_RX1P USB_SS_RX1NFCH-M3L NC pinLP23T61 T19R1702 10K_0402_5% FCH_PCIE_WAKE#K19 J19 J21PS2_DAT/SDA4/GPIO187 PS2_CLK/CEC/SCL4/GPIO188 SPI_CS2#/GBE_STAT2/GPIO166USB_SS_TX0P USB_SS_TX0N USB_SS_RX0P USB_SS_RX0NLP1+3VSGPIO189 GPIO190 &15& PXS_RST# &17,43& PXS_PWREN 1 1 1 1 1 2 2.2K_ 2.2K_ 10K_0402_5% FCH_SMCLK0 FCH_SMDAT0 WD_PWRGD &30& VGA_GATE# 2 G 3 D PX@ 0_ 0_ PX@ 1 PX@ 1 R96 R97D21 C20 D23 C22PS2KB_DAT/GPIO189 PS2KB_CLK/GPIO190 PS2M_DAT/GPIO191 PS2M_CLK/GPIO192EMBEDDED CTRLR171 R172 R175 R173 R176Q112 S 2N7002K_SOT23-32 8.2K_0402_5% WLAN_CLKREQ# 2 8.2K_0402_5% LAN_CLKREQ#+3VALW +3VALW2 UMA@ 110K_0402_5% R685 2 UMA@ 1410K_0402_5% R684F21 E20 F20 A22 E18 A20 J18 H18 G18 B21 K18 D19 A18 C18 B19 B17 A24 D17KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217 KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226 S IC 218- HUDSON-M3L FCBGA 656P C38SCL2/GPIO193 SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196 EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 EC_PWM3/EC_TIMER3/GPIO200 KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO2081 1 1 12 2 2 21EC_PWM2EC_PWM2 &14&strap pin4R166 1 R168 1 R177 1 R178 1 R180 1 @ @2 10K_ 10K_ 2.2K_ 10K_ 10K_0402_5%FCH_SMCLK1 FCH_SMDATA1 PX@ 1 10K_0402_5% R682 PX@ 1 2 10K_0402_5% R683 EC_RSMRST# HDA_BITCLK HDA_SDIN0 2GPIO189 GPIO190BOARD Config.GPIO189 0 0 1 1GPIO190 0 1 0 1Function PX4 Full PX4 low UMA Low UMA FullSecurity Classification Issued Date Compal Secret DataDeciphered DateCompal Electronics, Inc.TitleR182 1 PX@2 10K_0402_5% PEG_CLKREQ#_RTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.C DFCH-ACPI/USB/HDA/GPIOSize Document Number Custom Date:LA8681PSheetERev 0.1 12 of 48Wednesday, November 30, 2011ABABCDE+3VS L4 1 2 MBK1608221YZF_2P +VDDPL_33_SYS +3VS 1 R185 2 0_0603_5% +VDDIO_33_PCIGP 22U_V6M 0.1U_K 0.1U_K 0.1U_K C176 C178 C187 C179U2C+1.1VS1007mAHUDSON-2 C183 0.1U_K VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9 VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8 T14 T17 T20 U16 U18 V14 V17 V20 Y17+VCC_VDDCR_11 C184 0.1U_K C185 1U_V6K C186 1U_V6K C177 10U_V6M220 ohm102mAAB17 AB18 AE9 AD10 AG7 AC13 AB12 AB13 AB14 AB16 VDDIO_33_PCIGP_1 VDDIO_33_PCIGP_2 VDDIO_33_PCIGP_3 VDDIO_33_PCIGP_4 VDDIO_33_PCIGP_5 VDDIO_33_PCIGP_6 VDDIO_33_PCIGP_7 VDDIO_33_PCIGP_8 VDDIO_33_PCIGP_9 VDDIO_33_PCIGP_10 VDDPL_33_SYS VDDPL_33_DAC VDDPL_33_ML VDDAN_33_DAC VDDPL_33_SSUSB_S VDDPL_33_USB_S VDDPL_33_PCIE1 R1842 0_0805_5%111122PCI/GPIO I/O2222CORE S0C1812.2U_V6MC1820.1U_K1111111222221+1.1VS_CKVDD +1.1VS_CKVDD C189 0.1U_K C190 0.1U_K C191 1U_V6K C192 1U_V6K C193 22U_V6Mdel +VDDPL_33_MLDAC power plane47mA340mAH26 J25 K24 L22 M22 N21 N22 P22 CLKGEN I/Odemo board connect to GNDVDDPL_33_SSUSB_S For Hudson3 USB3.0 only For Hudson2, connect to GND+VDDPL_33_SSUSB_S +VDDPL_33_USB_S +VDDPL_33_PCIE+VDDPL_33_SYSH2420mAV22+1.1VS 42ohm @ 100MHz 1 2 R187 0_0603_5%112mAU221111130mAT2211mAL182222214mAD711mAAH291088mAVDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8 AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27 +VDDAN_11_PCIE C195 0.1U_K C196 1U_V6K C197 22U_V6M PCI EXPRESS+VDDAN_11_PCIELDO_CAP: Internally generated 1.8V supply for the RGB outputs+VDDPL_33_SATA @ 1 C19412mAAG28 2 M31 2.2U_V4Z+1.1VS 42ohm @ 100MHz 1 2 R191 0_0805_5%VDDPL_33_SATA LDO_CAP VDDPL_11_DAC111del +FCH_VDDAN_33_DAC power planeSERIAL ATAdemo board connect to GND7mAV212221337mAVDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9 VDDAN_11_SATA_10 VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8 AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19+AVDD_SATA C203 0.1U_K C204 1U_V6K C205 1U_V6K C206 22U_V6M226mAMAIN LINK Y22 V23 V24 V25 VDDAN_11_ML_1 VDDAN_11_ML_2 VDDAN_11_ML_3 VDDAN_11_ML_4+1.1VS 42ohm @ 100MHz 1 2 R194 0_0805_5%1111222222AB10 AB11 AA11 1 R196 L8 +3VALW L6 1 2 +VDDPL_33_SSUSB_S MBK1608221YZF_2P C198 2.2U_V6M 1 2 FBMA-L11-LMA30T_0805 +VDDAN_33_USB 10U_V6M 10U_V6M C212 C213 C214 1U_V6K C215 1U_V6K C216 0.1U_K 2 0_0402_5% AA9 AA10VDDIO_33_GBE_S GBE LAN VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2 VDDIO_GBE_S_1 VDDIO_GBE_S_2 VDDAN_33_USB_S_1 VDDAN_33_USB_S_2 VDDAN_33_USB_S_3 VDDAN_33_USB_S_4 VDDAN_33_USB_S_5 VDDAN_33_USB_S_6 VDDAN_33_USB_S_7 VDDAN_33_USB_S_8 VDDAN_33_USB_S_9 VDDAN_33_USB_S_10 VDDAN_33_USB_S_11 VDDAN_33_USB_S_12 VDDAN_11_USB_S_1 VDDAN_11_USB_S_2 USB+3VALW 1 R195 2 0_0402_5%59mAN18 L19 M18 V12 V13 Y12 Y13 W11 C207 1U_V6K+VDDIO_33_S C208 1U_V6K C209 2.2U_V6M+3VALW470mAG7 H8 J8 K8 K9 M9 M10 N9 N10 M12 N12 M113.3V_S5 I/O111222220 ohm/2A+3VALW L9 1 2 MBK1608221YZF_2P111115mAVDDXL_33_S G24 C217 2.2U_V6M+VDDXL_3.3V220 ohm1122222220 ohm1+VDDXL_3.3V Tie to +3.3V_S5 rail if USB3 W otherwise, tie to +3.3V_S0 rail. Hudson-2 designs: Tie to +3.3V_S0 rail.C2000.1U_K222+1.1VALW L11 1 2 MBK1608221YZF_2P +VDDAN_11_USB_S C219 2.2U_V6M C220 C234 0.1U_K 0.1U_K140mAU12 U13 VDDCR_11_S_1 VDDCR_11_S_2+1.1VALW +VDDCR_1.1V 1 R197 2 0_0603_5%187mAN20 M20 C221 1U_V6K+VDDAN_33_USB L7 +VDDPL_33_USB_S 1 2 MBK1608221YZF_2P C210 2.2U_V6M C2113220 ohmC2221U_V6K111@11220 ohm2220.1U_K31122+1.1VALW L13 1 2 MBK1608221YZF_2PAdd C234 follow AMD reccommandation 10/28+VDDCR_11V_USB C225 0.1U_K2242mAT12 T13 VDDCR_11_USB_S_1 VDDCR_11_USB_S_2 VDDPL_11_SYS_S+1.1VALW70mAJ24 C226 2.2U_V6M C228+VDDPL_11_SYS_S 0.1U_K220 ohmL14 1 2 MBK1608221YZF_2PC22310U_V6MC2240.1U_K111220 ohm11+3VS L10 +VDDPL_33_PCIE 1 2 MBK1608221YZF_2P 22222220 ohm+3VALW +VDDAN_33_HWM 1 R198 2 0_0402_5%+FCH_VDD_11_SSUSB_SUSB SSC2182.2U_V6M282mA+VDDAN_11_SSUSB C229 1U_V6K C230 0.1U_K C231 0.1U_K P16 M14 N14 P13 P14 VDDAN_11_SSUSB_S_1 VDDAN_11_SSUSB_S_2 VDDAN_11_SSUSB_S_3 VDDAN_11_SSUSB_S_4 VDDAN_11_SSUSB_S_5 VDDAN_33_HWM_S12mAM8 C232 2.2U_V6M C233140mils1 R199 2 0_0603_5%211AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.0.1U_K111@2 +3VS L12 +VDDPL_33_SATA 1 2 MBK1608221YZF_2P22424mAN16 N17 P17 M17 VDDCR_11_SSUSB_S_1 VDDCR_11_SSUSB_S_2 VDDCR_11_SSUSB_S_3 VDDCR_11_SSUSB_S_42@2+3VS 1 2 R200 0_ 2.2U_V6M VDDIO_AZ_S should be tied to +3.3/1.5V_S5 rail if Wake on Ring is supported426mAVDDIO_AZ_S POWER AA4+VDDIO_AZ C236 1C2272.2U_V6M220 ohm41+1.1VALW2L1511 R201 2 0_0603_5%+VDDCR_11_SSUSB C237 10U_V6M C238 1U_V6K C239 0.1U_K C240 0.1U_KS IC 218- HUDSON-M3L FCBGA 656P C38 12FBMA-L11-LMA30T_080542 ohm/4A1112222Security Classification Issued Date Compal Secret DataDeciphered DateCompal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C DFCH PWRSize Document Number Custom Date:LA8681PSheetERev 0.1 13 of 48Tuesday, November 29, 201154321DEBUG STRAPSU2E HUDSON-2 A3 A33 B7 B13 D9 D13 E5 E12 E16 E29 F7 F9 F11 F13 F16 F17 F19 F23 F25 F29 G6 G16 G32 H12 H15 H29 J6 J9 J10 J13 J28 J32 K7 K16 K27 K28 L6 L12 L13 L15 L16 L21 M13 M16 M21 M25 N6 N11 N13 N23 N24 P12 P18 P20 P21 P31 P33 R4 R11 R25 R28 T11 T16 T18 N8 K25 H25 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSAN_HWM VSSXL VSSPL_SYS EFUSE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33 T21 L28 K33 N28 R6STRAP PINSPCI_CLK1 PULL HIGHALLOW PCIE GEN2DEFAULTFCH HAS 15K INTERNAL PU FOR PCI_AD[27:23] PCI_CLK3USE DEBUG STRAPSPCI_CLK4NON_FUSION CLOCK MODELPC_CLK0_ECEC ENABLEDLPC_CLK1CLKGEN ENABLEDDEFAULTEC_PWM2LPC ROMRTC_CLKS5 PLUS MODE DISABLEDDEFAULTPCI_AD27 PULL HIGHUSE PCI PLLDEFAULTPCI_AD26DISABLE ILA AUTORUNDEFAULTPCI_AD25USE FC PLLDEFAULTPCI_AD24USE DEFAULT PCIE STRAPSDEFAULTPCI_AD23DISABLE PCI MEM BOOTDEFAULTDDPULL LOWFORCE PCIE GEN1IGNORE DEBUG STRAPDEFAULTFUSION CLOCK MODEDEFAULTEC DISABLEDDEFAULTCLKGEN DISABLESPI ROMS5 PLUS MODE ENABLEDPULL LOWBYPASS PCI PLLENABLE ILA AUTORUNBYPASS FC PLLUSE EEPROM PCIE STRAPSENABLE PCI MEM BOOTDEFAULT+3VS R202 10K_0402_5%+3VS R203 10K_0402_5%+3VS R204 10K_0402_5%+3VALW R205 10K_0402_5%+3VALW R206 10K_0402_5%+3VALW R207 10K_0402_5%+3VALW R208 10K_0402_5%111111GROUND@ 2@ 2@ 2@ 21&10& PCI_AD27CC&10& PCI_AD26 &10& PCI_AD25 &10& PCI_AD2422&10& PCI_CLK1 &10& PCI_CLK3 &10& PCI_AD23 &10& PCI_CLK4 &10,30& CLK_PCI_EC 1 &10& LPC_CLK1 &12& EC_PWM2 &10,30& RTC_CLK R214 10K_0402_5% R215 10K_0402_5% R216 10K_0402_5% R217 10K_0402_5% R218 10K_0402_5% R219 2.2K_0402_5% R220 2.2K_0402_5% @ 2 R209 2.2K_0402_5% R210 2.2K_0402_5% R211 2.2K_0402_5% R212 2.2K_0402_5% R213 2.2K_0402_5%2111@ 2@ 2@ 2@ 2111111@ 2@ 2@ 2222VSSPL_DAC VSSAN_DAC VSSANQ_DAC VSSIO_DACS IC 218- HUDSON-M3L FCBGA 656P C38A A2B11BSecurity Classification Issued DateCompal Secret DataDeciphered DateCompal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2FCH-VSS/StrapSize B Date: Document NumberLA8681PWednesday, November 30, 2011 Sheet1Rev 0.1 14 of 4854321&6& PCIE_CTX_GRX_P[3..0] &6& PCIE_CTX_GRX_N[3..0]PCIE_CTX_GRX_P[3..0] PCIE_CTX_GRX_N[3..0]U6A PX@PCIE_CRX_GTX_P[3..0] PCIE_CRX_GTX_N[3..0]PCIE_CRX_GTX_P[3..0] &6& PCIE_CRX_GTX_N[3..0] &6&LVDS InterfacePCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 TXCLK_UP_DPF3P TXCLK_UN_DPF3N TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N TXOUT_U3P TXOUT_U3N LVTMDP AK35 AL36 AJ38 AK37 AH35 AJ36 AG38 AH37 AF35 AG36CPCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0DAA38 Y37 Y35 W36 W38 V37 V35 U36 U38 T37 T35 R36 R38 P37PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_RX4P PCIE_RX4N PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N PCIE_RX13P PCIE_RX13N PCIE_RX14P PCIE_RX14N PCIE_RX15P PCIE_RX15NPCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N PCIE_TX4P PCIE_TX4N PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N PCIE_TX13P PCIE_TX13N PCIE_TX14P PCIE_TX14N PCIE_TX15P PCIE_TX15NY33 Y32PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N00.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K 0.1U_K2 2 2 2 2 2 2 21 C241 PX@ 1 C242 PX@ 1 C243 PX@ 1 C244 PX@ 1 C245 PX@ 1 C246 PX@ 1 C247 PX@ 1 C248 PX@U6G PX@DPCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3W33 PCIE_CRX_C_GTX_P1 W32 PCIE_CRX_C_GTX_N1 U33 PCIE_CRX_C_GTX_P2 U32 PCIE_CRX_C_GTX_N2 U30 PCIE_CRX_C_GTX_P3 U29 PCIE_CRX_C_GTX_N3 T33 T32 T30 T29 P33 P32 P30 P29 N33 N32 N30 N29 L33 L32 L30 L29 K33 K32 J33 J32 K30 K29 H33 H32LVDS CONTROLVARY_BL DIGONAK27 AJ27PCI EXPRESS INTERFACECP35 N36 N38 M37 M35 L36 L38 K37 K35 J36 J38 H37BTXCLK_LP_DPE3P TXCLK_LN_DPE3N TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N TXOUT_L3P TXOUT_L3NAP34 AR34 AW37 AU35 AR37 AU39 AP35 AR35 AN36 AP37ROBSON XT M2BH35 G36 G38 F37 F35 E37R221 2@1 0_0402_5%+3VGSCLOCK &10& CLK_PCIE_VGA &10& CLK_PCIE_VGA# &12,17,43& VGA_PWRGD CLK_PCIE_VGA AB35 CLK_PCIE_VGA# AA36 R222 @ 2 R224 2 PX@ 1 10K_0402_5% GPU_RST# 1 0_ AH16 AA30 PCIE_REFCLKP PCIE_REFCLKN CALIBRATION PCIE_CALRPA5 &12& PXS_RST# &10,29& APU_PCIE_RST# Y30 Y29 1.27K_ PX@ 2K_ PX@ 2 R223 2 R225 +1.0VGS 2 1 B A PU7 Y 4 GPU_RST#G PX@ MC74VHC1G08DFT2G SC70 5PAPWRGOOD PERSTBPCIE_CALRN3Security Classification Issued DateCompal Secret DataDeciphered DateCompal Electronics, Inc.TitlePX@ ROBSON XT M2 R226 100K_THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.4 3 2ATI_RobsonXT_M2_PCIE/LVDSSize B Date: Document NumberLA8681PWednesday, November 30, 2011 Sheet1Rev 0.1 15 of 48554321U6BCONFIGURATION STRAPSALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESETTXCAP_DPA3P TXCAM_DPA3N MUTI GFX DPA TX0P_DPA2P TX0M_DPA2N TX1P_DPA1P TX1M_DPA1N AU24 AV23 AT25 AR24 AU26 AV25 AT27 AR26 AR30 AT29 AV31 AU30 AR32 AT31 AT33 AU32 AU14 AV13 AT15 AR14 AU16 AV15 AT17 AR16 AU20 AT19 AT21 AR20 AU22 AV21 AT23 AR22 1 1 @ R250 10K_0402_5% @ R265 10K_ 2 2 1U_V6K PX@ C274 10U_V6M PX@ C273 0.1U_K PX@ CVGS STRAPS TX_PWRS_ENB TX_DEEMPH_EN RSVD RSVD BIF_VGA DIS RSVD BIOS_ROM_EN ROMIDCFG(2:0) VIP_DEVICE_STRAP_ENA RSVD RSVD AUD[1] AUD[0] +3VGS +3VGS PIN GPIO0 GPIO1 GPIO2 GPIO8 GPIO9 GPIO21 GPIO_22_ROMCSB GPIO[13:11] V2SYNC H2SYNC GENERICC HSYNC VSYNC DESCRIPTION OF DEFAULT SETTINGS PCIE FULL TX OUTPUT SWING PCIE TRANSMITTER DE-EMPHASIS Advertises PCIE speed when compliance test RESERVED VGA ENABLED RESERVED ENABLE EXTERNAL BIOS ROMRECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE RECOMMENDED SETTINGS0: 50% swing 1: Full swing 0: disable 1: enable 0: 2.5GT/s 1: 5GT/sX X 0 0 0 0DD&20& VRAM_ID0 &20& VRAM_ID1 &20& VRAM_ID2AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12 AJ21 AK21DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 SWAPLOCKA SWAPLOCKBTX2P_DPA0P TX2M_DPA0N TXCBP_DPB3P TXCBM_DPB3N TX3P_DPB2P TX3M_DPB2N TX4P_DPB1P TX4M_DPB1N TX5P_DPB0P TX5M_DPB0N TXCCP_DPC3P TXCCM_DPC3N TX0P_DPC2P TX0M_DPC2N DPC TX1P_DPC1P TX1M_DPC1N TX2P_DPC0P TX2M_DPC0N TXCDP_DPD3P TXCDM_DPD3N TX3P_DPD2P TX3M_DPD2N DPD TX4P_DPD1P TX4M_DPD1N TX5P_DPD0P TX5M_DPD0NDPB0: disable 1: enableX XXX 0 0 0SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT IGNORE VIP DEVICE STRAPSAUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI11I2CAMD RESERVED CONFIGURATION STRAPS2 L16 PX@ BLM15BD121SN1D_0402STRAPS+3VGSCAK26 AJ26SCL SDA GENERAL PURPOSE I/O R RB G GB B BB HSYNC VSYNC RSET AVDD AVSSQ VDD1DI VSS1DI R2/NC R2B/NC G2/NC G2B/NC B2/NC B2B/NC C/NC Y/NC COMP/NC DAC2 H2SYNC/GENLK_CLK V2SYNC/GENLK_VSYNC VDD2DI/NC VSS2DI/NC AD29 AC29 AG31 AG32 AG33 AD33 AF33 AA29 AD39 AD37 AE36 AD35 AF37 AE38 AC36 AC38 AB34 AD34 AE34 AC33 AC34 AC30 AC31 AD30 AD31 AF30 AF31 AC32 AD32 AF32 R238 1 PX@ +AVDD +VDD1DIALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP &LOW& AND NOT CONFLICT DURING RESETGPIO21 H2SYNC GENERICC GPIO2 GPIO8C10K_K_K_K_K_K_K_K_K_0402_5%@ 1 2 1 PX@ 2 1 PX@ 2 R1.0 1 1 1 @ @ @ 2 2 2 2 2 2R229 GPU_GPIO0 R230 GPU_GPIO1 R231 GPU_GPIO2 R232 GPU_GPIO5 R234 GPU_GPIO8 R236 GPU_GPIO9 R237 GPU_GPIO11 R239 GPU_GPIO12 R240 GPU_GPIO13 &43& GPU_VID0 T50 R241 1 @ &43& GPU_VID1 RB751V_SOD323 D2 @ 1 T49&30,38& ACIN2GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 VGA_SMB_DA2 VGA_SMB_CK2 GPU_GPIO5 GPU_GPIO_6 R02 GPU_GPIO8 GPU_GPIO9 GPU_GPIO11 GPU_GPIO12 GPU_GPIO13 GPU_VID0 GPIO_16 2 10K_0402_5% GPU_VID1 GPIO21_BBEN PEG_CLKREQ# GPIO24_TRSTB GPIO25_TDI GPIO26_TCK GPIO27_TMS GPIO28_TDO1 PX@ @ 1 @ 1+3VGS 10K_K_K_K_ 1 1 1 @ @ @ @ 2 R242 2 R243 2 R244 2 R245 GPIO24_TRSTB GPIO25_TDI GPIO27_TMS GPIO26_TCK &12& PEG_CLKREQ#T51T52BAH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13 AM23 AN23 AK23 AL24 AM24 AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24 AK2410U_V6M0.1U_K C435GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6 HPD1111DAC1222TX_PWRS_ENBTransmitter Power Saving Enable GPIO0 0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop) PCI Express Transmitter De-emphasis Enable GPIO1 0: Tx de-emphasis diabled for mobile mode 1: Tx de-emphasis enabled (Defailt setting for desktop)2 499_0402_1%TX_DEEMPH_EN(1.8V@65mA AVDD) (1.8V@100mA VDD1DI) 10.1U_K PX@ C276 1U_V6K PX@ C277 1 1 10U_V6M PX@ C278 1 +3VGS 2 2 +1.8VGS L17 PX@ BLM15BD121SN1D_040222Internal VGA Thermal Sensor+3VGS R247 10K_0402_5%1 R246 10K_1+VDD2DI GENLK_CLK GENLK_VSYNC T53 T54 C434 12mA1U_V4Z C429 1 1+1.8VGS Robson@ L28 1 2 BLM15BD121SN1D_0402VGA_SMB_CK2 PX@ VGA_SMB_DA22126 5EC_SMB_CK2&5,29,30&BQ17A DMN66D0LDW-7_SOT363-6 43EC_SMB_DA2&5,29,30&+VDD2DIRobson@ Robson@ Robson@ 2 2 2PX@ Q17B DMN66D0LDW-7_SOT363-6+1.8VGS +1.8VGS L18 PX@ 2 1 BLM15BD121SN1D_0402 PX@ 2 R248 PX@ 2 R2490.60 V level, Please VREFG Divider ans cap close to ASIC1 499_ 249_0402_1% +DPLL_PVDD AM32 AN32 +DPLL_VDDC AN31 XTALIN XTALOUT AV33 AU34 AW34 +VREFG_GPU AH13 VREFGA2VDD/NC A2VDDQ/NC A2VSSQ/TSVSSQ R2SET/NC DPLL_PVDD DPLL_PVSS DDC/AUX PLL/CLOCK DPLL_VDDC XTALIN XTALOUT XO_IN XO_IN2 AUX2P AUX2N DDCCLK_AUX3P DDCDATA_AUX3N DDC1CLK DDC1DATA AUX1P AUX1N DDC2CLK DDC2DATA+A2VDD +A2VDDQ +A2VDD75mA10U_V6M PX@ C280 1U_V6K PX@ C281 0.1U_K PX@ C282 1 1+DPLL_PVDD100mAC437 1 0.1U_K C395 1 1U_V4Z C380 1U_V4Z C436 R330 1 Robson@2 715_1222AM26 AN26 AM27 AL27 AM19 AL19 AN20 AM20 AL30 AM30 AL29 AM29 AN21 AM21 AJ30 AJ31 AK30 AK29 +A2VDDQRobson@ Robson@ Robson@ 2 2 2+1.0VGS L19 PX@ 2 1 BLM15BD121SN1D_0402125mA10U_V6M PX@ C284 1U_V6K PX@ C285 0.1U_K PX@ C287 1 1+DPLL_VDDC1222AF29 AG29 T58 TS_FDO AK32 AL31 PX@ L20 +1.8VGS 1 2 BLM15BD121SN1D_0402DPLUS DMINUS TS_FDO TS_A/NC TSV}