From Wikipedia, the free encyclopedia
Main article:
is 's line of low-power, low-cost and low-performance
. Atom, with codenames of
and , was first announced on March 2, 2008.
For Nettop and Netbook Atom Microprocessors after Diamondville, the memory and graphics controller are moved from the
to the CPU. This explains the drastically increased transistor count for post-Diamondville Atom microprocessors.
All models support: , , , , , , XD bit (an
implementation),
These models do not support
Transistors: 47 million
Die size: 25.96 mm? (3.27 × 7.94)
Package size: 22 mm × 22 mm
Steppings: C0
Release date
SLB6Z (C0)
June 3, 2008
All models support: , , , , , , XD bit (an
implementation),
These models do not support
and memory controller are integrated into the processor.
Transistors: 123 million
Die size: 66 mm? (9.56 × 6.89)
Package size: 22 mm × 22 mm
Release date
SLBMH (A0)
0.8–1.175 V
FC-BGA 559
January 4, 2010
SLBXD (A0)
1 × DDR2-800
0.8–1.175 V
FC-BGA 559
June 21, 2010
All models support: , , , , , , XD bit (an
implementation),
These models do not support
Transistors: 2 × 47 million
Die size: 2 × 25.96 mm?
Package size: 22 mm × 22 mm
Steppings: C0
Release date
SLG9Y (C0)
June 3, 2008
All models support: , , , , , , XD bit (an
implementation),
These models do not support
and memory controller are integrated into the processor.
Transistors: 176 million
Die size: 87 mm? (9.56 × 9.06)
Package size: 22 mm × 22 mm
Release date
SLBLA (B0)
1 × DDR2-800
0.8–1.175 V
FC-BGA 559
December 21, 2009
SLBXC (B0)
2 × 512 KB
1 × DDR2-800
1 × DDR3-800
0.8–1.175 V
FC-BGA 559
June 21, 2010
All models support: , , , , , , XD bit (an
implementation),
(D2550, D2560, D2700, D2701 only),
(D2560 only)
These models do not support .
-based Intel /
and memory controller are integrated into the processor.
Transistors: ?
Die size: ?
Package size: 22 mm × 22 mm
Release date
SR0D8 (B2)
SR0W0 (B3)
1 × DDR3-800
1 × DDR3-1066
0.91–1.21 V
FC-BGA 559
November, 2011
SR0QB (B2)
SR0VY (B3)
2 × 512 KB
1 × DDR3-800
1 × DDR3-1066
0.91–1.21 V
FC-BGA 559
March, 2012
SR0QD (B2)
SR0W4 (B3)
2 × 512 KB
1 × DDR3-800
1 × DDR3-1066
0.91–1.21 V
FC-BGA 559
October, 2012
SR0D9 (B2)
2 × 512 KB
1 × DDR3-800
1 × DDR3-1066
0.91–1.21 V
FC-BGA 559
November, 2011
SR0W6 (unknown)
unknown MHz
2 × 512 KB
unknown–unknown V
All models support: , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation),
These models do not support , , or .
Transistors: 47 million
Die size: 26 mm?
Package size: 22 mm × 22 mm
Release date
SLB73 (C0)
June 3, 2008
SLGL9 (C0)
February 6, 2009
All models support: , , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation),
These models do not support
and are limited to 2 of memory.
and memory controller are integrated into the processor, but graphics sometimes disabled in favor of discrete video chip.
Transistors: 123 million (a significant number of these are from the memory controller and GMA 3150)
Die size: 66 mm?
Package size: 22 mm × 22 mm
Release date
SLC4C (A0)
1 × DDR2-667
1 × DDR3-800
0.8–1.175 V
FC-BGA 559
SLBMG (A0)
1 × DDR2-667
0.8–1.175 V
FC-BGA 559
December 21, 2009
SLBX9 (A0)
1 × DDR2-800
1 × DDR3-800
0.8–1.175 V
FC-BGA 559
June 1, 2010
SLBMF (A0)
1 × DDR2-667
0.8–1.175 V
FC-BGA 559
March 1, 2010
SLBX5 (A0)
1 × DDR2-800
1 × DDR3-800
0.8–1.175 V
FC-BGA 559
June 1, 2010
All models support: , , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation),
These models do not support
based on PowerVR and memory controller are integrated into the processor.
Transistors: ? million
Die size: ?
Package size: ?
Release date
Atom N2100
SR0DC (B2)
1 × DDR3-800
FC-BGA 559
All models support: , , , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation)
These models do not support
GPU and memory controller are integrated into the processor die
Transistors: 176 million
Die size: 87 mm?
Package size: 22 mm × 22 mm
Release date
SLBXF (B0)
1 × DDR2-800
1 × DDR3-800
0.8–1.175 V
FC-BGA 559
August 23, 2010
SLBXE (B0)
2 × 512 KB
1 × DDR2-800
1 × DDR3-800
0.8–1.175 V
FC-BGA 559
March 1, 2011
All models support: , , , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation)
These models do not support
Die size: ? mm?
and memory controller are integrated into the processor.
Transistors: ? million
Package size: 22 × 22 mm
Release date
SR0DB (B2)
SR0W2 (B3)
1 × DDR3-800
0.91–1.21 V
FC-BGA 559
December, 2011
SR0DA (B2)
SR0W1 (B3)
2 × 512 KB
1 × DDR3-1066
0.91–1.21 V
FC-BGA 559
December, 2011
All models support: , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation)
Models Z520, Z520PT, Z530, Z530P, Z540, Z550 and Z560 support
Models Z500, Z510P, Z510PT, and Z515 support Hyper-Threading only
Model Z515 supports Intel Burst Performance Technology
Transistors: 47 million
Die size: 26 mm?
Package size: 13 mm × 14 mm / 22 mm × 22 mm(Processors ending with the P or PT sSpec number)
Steppings: C0
Release date
SLB6Q (C0)
0.712–1.1 V
April 2, 2008
SLB2C (C0)
0.75–1.1 V
April 2, 2008
SLGPQ (C0)
0.8–1.1 V
March 2, 2009
SLGPR (C0)
0.75–1.1 V
March 2, 2009
SLGMG (C0)
0.712–1 V
April 8, 2009
SLB2H (C0)
0.75–1.1 V
April 2, 2008
SLGPP (C0)
0.9–1.1 V
March 2, 2009
SLB6P (C0)
0.75–1.1 V
April 2, 2008
SLGPN (C0)
0.8–1.1 V
March 2, 2009
SLB2M (C0)
0.75–1.1 V
April 2, 2008
SLGPT (C0)
0.75–1.1 V
April 8, 2009
SLH63 (C0)
0.75–1.1 V
All models support: , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation), . All except Z605 support Intel Burst Performance Technology (BPT).
GPU and memory controller are integrated onto the processor die
Transistors: 140 million
Die size: 7.34 mm × 8.89 mm = 65.;mm?
Package size: 13.8 mm × 13.8 × 1.0 mm
Steppings: C0
Release date
SLBZP (C0)
1 × LPDDR-400
May 4, 2010
SLC3C (C0)
1 × DDR-400
1 × DDR2-800
FC-BGA 518
May 4, 2010
SLBZQ (C0)
1 × DDR-400
1 × DDR2-800
FC-BGA 518
May 4, 2010
SLBZN (C0)
1 × DDR-400
1 × DDR2-800
FC-BGA 518
May 4, 2010
SLBZL (C0)
1 × DDR2-800
FC-BGA 518
May 4, 2010
SLBZE (C0)
1 × DDR-400
1 × DDR2-800
FC-BGA 518
May 4, 2010
SLBZD (C0)
1 × DDR2-800
FC-BGA 518
May 4, 2010
All models support: , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation), Intel Burst Performance Technology (BPT).
Model Z2610 supports
GPU and memory controller are integrated onto the processor die
Package size: 12 mm × 12 × 1.0 mm
Steppings: D1
Currently used in the
smartphone.
Release date
SR0YF (D1)
SR0Z5 (D1)
2 × LPDDR2-800
0.3–1.2 V
January 2013
SR0PR (D1)
SR0PS (D1)
SR0PV (D1)
SR0TM (D1)
SR0U6 (D1)
SR0VZ (D1)
SR114 (D1)
SR118 (D1)
1.3-1.6 GHz
2 × LPDDR2-800
0.3–1.2 V
January 2012
SR0U7 (D1)
SR0ZK (D1)
SR111 (D1)
SR117 (D1)
1.3-2.0 GHz
2 × LPDDR2-800
0.3–1.2 V
Atom Z2610
SR0PT (D1)
1.3-1.6 GHz
2 × LPDDR2-800
All models support: , , , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation), , , Intel Burst Performance Technology (BPT).
Z3480 also supports .
GPU ( G6400) and memory controller are integrated onto the processor die
Package size: 12 mm × 12 × 1.0 mm
Release date
SR1WR (B1)
SR20G (B1)
SR20U (B1)
400-457 MHz
2 × LPDDR3-1066
March 2014
SR1WS (B1)
SR20F (B1)
457-533 MHz
2 × LPDDR3-1066
March 2014
All models support: , , , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation), , , Intel Burst Performance Technology (BPT), .
GPU ( G6430) and memory controller are integrated onto the processor die
Package size: 14 mm × 14 × 1.0 mm
Release date
SR1YR (B0)
2 × LPDDR3-1600
SR1WW (B0)
SR1WX (B0)
457–533 MHz
2 × LPDDR3-1600
457–640 MHz
2 × LPDDR3-1600
SR1WU (B0)
SR1WV (B0)
457–533 MHz
2 × LPDDR3-1600
457-640 MHz
2 × LPDDR3-1600
All models support: , , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), Intel Burst Performance Technology (BPT), ,
(based on Silvermont's specs)
GPU () and memory controller are integrated onto the processor die
SoFIA 3G – R SoC with Silvermont CPU has Integrated HSPA+ A-GOLD 620: 2G/3G RF, CNV, PMU, Audio (Atom x3-C3130 & Atom x3-C3230RK)
SoFIA LTE (W) with Airmont CPU has Integrated LTE Cat. 4 (XG726-based), SMARTi(TM) 4.5, LnP/ CG2000, PMIC (Atom x3-C3440 & C3445)
Package size: - mm
Connectivity
Release date
Mali 400 MP2 (dual core)
1×32 LPDDR2 800
2G/3G, GPS, Bluetooth & WiFi
Mali 450 MP4 (quad core)
1×32 LPDDR2/3
DDR3/DDR3L 1333
Mali 450 MP4 (quad core)
1×32 LPDDR2/3
DDR3/DDR3L 1333
2G/3G, GPS, Bluetooth & WiFi
Mali T720 MP2 (dual core)
1×32 LPDDR2/3 1066
Mali T720 MP2 (dual core)
1×32 LPDDR2/3 1066
2G/3G/4G LTE, GPS, Bluetooth & WiFi
All models support: , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation), . All except Z605 support Intel Burst Performance Technology (BPT).
GPU and memory controller are integrated onto the processor die
Transistors: 140 million
Die size: 7.34 mm × 8.89 mm = 65.;mm?
Package size: 13.8 mm × 13.8 × 1.0 mm
Steppings: C0
Release date
SLC2Q (C0)
1 × DDR2-800
FC-BGA 518
April 11, 2011
SLC2P (C0)
1 × DDR2-800
FC-BGA 518
April 11, 2011
All models support: , , , , , Enhanced Intel
Technology (EIST), XD bit (an
implementation), , Intel Burst Performance Technology (BPT).
GPU and memory controller are integrated onto the processor die
Package size: 13.8 mm × 13.8 × 1.0 mm
Steppings:B1, C0
Release date
SR161 (B1)
2 × LPDDR2-1066
0.3–1.2 V
February 25, 2013
SR145 (B1)
2 × LPDDR2-1066
0.3–1.2 V
February 25, 2013
SR12U (C0)
SR12V (C0)
SR146 (B1)
2 × LPDDR2-1066
0.3–1.2 V
February 25, 2013
SR0WW (C0)
SR0Z4 (C0)
2 × LPDDR2-800
September 27, 2012
No official TDP available. For power data see
page 129-130.
All models support: , , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), Intel Burst Performance Technology (BPT), , .
GPU and memory controller are integrated onto the processor die
GPU is based on
, with 4 execution units, and supports DirectX 11, OpenGL 4.0, OpenGL ES 3.1 and OpenCL 1.1 (on Windows).
Package size: 17 mm × 17 × 1.0 mm
Release date
Atom Z3680
SR1S2 (B3)
(4 EUs)
311-667 MHz
2 × LPDDR3-1066
UTFCBGA1380
September 2013
Atom Z3680D
SR1S4 (B3)
HD Graphics (4 EUs)
313-688 MHz
1 × DDR3L-1333
UTFCBGA1380
September 2013
All models support: , , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), Intel Burst Performance Technology (BPT), , .
GPU and memory controller are integrated onto the processor die
GPU is based on
, with 4 execution units, and supports DirectX 11, OpenGL 4.0, OpenGL ES 3.1 and OpenCL 1.1 (on Windows).
Package size: 17 mm × 17 × 1.0 mm
Release date
SR1U7 (C0)
(4 EUs)
311-646 MHz
1 × DDR3L-1333 (64-bit)
UTFCBGA1380
SR1U9 (C0)
HD Graphics (4 EUs)
311-646 MHz
1 × DDR3L-1333 (32-bit)
UTFCBGA1380
SR1UB (C0)
HD Graphics (4 EUs)
311-646 MHz
1 × DDR3L-1333 (64-bit)
UTFCBGA592
SR1UD (C0)
HD Graphics (4 EUs)
311-646 MHz
1 × DDR3L-1333 (32-bit)
UTFCBGA592
SR20D (C0)
HD Graphics (4 EUs)
313-646 MHz
1 × DDR3L-1333 (64-bit)
UTFCBGA592
SR20E (C0)
HD Graphics (4 EUs)
313-646 MHz
1 × DDR3L-1333 (32-bit)
UTFCBGA592
SR1M5 (B2)
SR1RW (B3)
HD Graphics (4 EUs)
311-667 MHz
2 × LPDDR3-1066
UTFCBGA1380
September 2013
SR1M9 (B2)
SR1S0 (B3)
HD Graphics (4 EUs)
313-688 MHz
1 × DDR3L-1333
UTFCBGA1380
September 2013
SR1SP (C0)
HD Graphics (4 EUs)
311-778 MHz
2 × LPDDR3-1066
UTFCBGA1380
SR1ST (C0)
HD Graphics (4 EUs)
311-792 MHz
1 × DDR3L-1333
UTFCBGA1380
SR1M3 (B2)
SR1RU (B3)
HD Graphics (4 EUs)
311-667 MHz
2 × LPDDR3-1066
UTFCBGA1380
September 2013
SR1M7 (B2)
SR1RY (B3)
HD Graphics (4 EUs)
313-688 MHz
1 × DDR3L-1333
UTFCBGA1380
September 2013
SR1SM (C0)
HD Graphics (4 EUs)
311-778 MHz
2 × LPDDR3-1066
UTFCBGA1380
SR1SR (C0)
HD Graphics (4 EUs)
311-792 MHz
1 × DDR3L-1333
UTFCBGA1380
SR1V9 (C0)
HD Graphics (4 EUs)
313-833 MHz
2 × LPDDR3-1333
UTFCBGA1380
SR1SK (C0)
HD Graphics (4 EUs)
311-778 MHz
2 × LPDDR3-1066
UTFCBGA1380
All models support: , , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), 2 (VT-x with , FlexMigration, FlexPriority and VPID), .
GPU and memory controller are integrated onto the processor die
GPU is based on 8th generation () , with 12 (x5 models) or 16 (x7 models) execution units, and supports DirectX 11.2, OpenGL 4.3, OpenGL ES 3.1 and OpenCL 1.2 (on Windows).
Package size: 17 mm × 17 × 1.0 mm
Release date
SR29Z (C0)
(12 EUs)
200-500 MHz
1 × DDR3L-1600
UTFCBGA592
March 2015
HD Graphics 400
200-500 MHz
1 × DDR3L-1600
UTFCBGA592
February 2016
HD Graphics (12 EUs)
200-500 MHz
1 × DDR3L-1600
UTFCBGA592
February 2016
SR27N (C0)
SR2GN (C0)
HD Graphics (12 EUs)
200-600 MHz
2 × LPDDR3-1600
UTFCBGA1380
March 2015
HD Graphics 400
200-600 MHz
2 × LPDDR3-1600
UTFCBGA1380
February 2016
SR27M (C0)
SR29W (C0)
HD Graphics (16 EUs)
200-600 MHz
2 × LPDDR3-1600
UTFCBGA1380
March 2015
HD Graphics (16 EUs)
200-600 MHz
2 × LPDDR3-1600
UTFCBGA1380
February 2016
CPU core supports
architecture, , , , , , Enhanced Intel
Technology (EIST), , . It has 32K L1 Instruction Cache, 24K L1 Data Cache, 512K L2 Cache.
Peripherals include
(two video outputs),
(2GB max),
controller,
controller, 4 channels of
×1, and various legacy devices.
Package size: 22 mm × 22 mm
Steppings: B0
Temperature range: for (E620, E640, E660, E680): 0°C to +70°C, for (E620T, E640T, E660T, E680T): -40°C to +85°C.
Release date
SLH56 (B0)
SLJ32 (B1)
1 × DDR2-800
0.8–1.175 V
September 14, 2010
SLH5N (B0)
SLJ36 (B1)
1 × DDR2-800
0.8–1.175 V
FC-BGA 676
September 14, 2010
SLH55 (B0)
SLJ33 (B1)
1 × DDR2-800
0.8–1.175 V
FC-BGA 676
September 14, 2010
SLH5M (B0)
SLJ37 (B1)
1 × DDR2-800
0.8–1.175 V
FC-BGA 676
September 14, 2010
SLH54 (B0)
SLJ34 (B1)
1 × DDR2-800
0.8–1.175 V
FC-BGA 676
September 14, 2010
SLH5L (B0)
SLJ38 (B1)
1 × DDR2-800
0.8–1.175 V
FC-BGA 676
September 14, 2010
SLH94 (B0)
SLJ35 (B1)
1 × DDR2-800
0.8–1.175 V
FC-BGA 676
September 14, 2010
SLH95 (B0)
SLJ39 (B1)
1 × DDR2-800
0.8–1.175 V
FC-BGA 676
September 14, 2010
"" CPU with an Altera Field Programmable Gate Array (FPGA)
CPU core supports
architecture, , , , , , Enhanced Intel
Technology (EIST), , . It has 32K L1 Instruction Cache, 24K L1 Data Cache, 512K L2 Cache.
Peripherals include
(two video outputs),
(2GB max), HD Audio controller,
controller, 4 channels of
×1, and various legacy devices.
Package size: 37.5 mm × 37.5 mm
Steppings: B0
TDP without FPGA. Total package TDP depends on functions included in FPGA. Max. TDP 7 W.
Temperature range: for (E625C, E645C, E665C): 0°C to +70°C, for (E625CT, E645CT, E665CT): -40°C to +85°C.
Release date
SLH9Z (B0)
1 × DDR2-800
0.8–1.175 V
FC-BGA 1466
November 22, 2010
SLH9K (B0)
1 × DDR2-800
0.8–1.175 V
FC-BGA 1466
November 22, 2010
SLH9Y (B0)
1 × DDR2-800
0.8–1.175 V
FC-BGA 1466
November 22, 2010
SLH9J (B0)
1 × DDR2-800
0.8–1.175 V
FC-BGA 1466
November 22, 2010
SLH9X (B0)
1 × DDR2-800
0.8–1.175 V
FC-BGA 1466
November 22, 2010
SLH9H (B0)
1 × DDR2-800
0.8–1.175 V
FC-BGA 1466
November 22, 2010
All models support: , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), , , .
GPU and memory controller are integrated onto the processor die
GPU is based on
, with 4 execution units, and supports 2 displays, DirectX 11, OpenGL 4.0, OpenGL ES 3.1 and OpenCL 1.1 (on Windows).
Peripherals include
2.0, HD Audio controller,
with 2 ports, , and 4 lanes of
2.0, in x4, x2, and x1 configurations.
Package size: 25 mm × 27 mm
Release date
SR1RA (B3)
SR1XA (D0)
(4 EUs)
1 × DDR3L-1066
FC-BGA 1170
October 2013
All models support: , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), , , .
GPU and memory controller are integrated onto the processor die
GPU is based on
, with 4 execution units, and supports 2 displays, DirectX 11, OpenGL 4.0, OpenGL ES 3.1 and OpenCL 1.1 (on Windows).
Peripherals include
2.0, HD Audio controller,
with 2 ports, , and 4 lanes of
2.0, in x4, x2, and x1 configurations.
Package size: 25 mm × 27 mm
Release date
SR20Y (D0)
1 × DDR3L-1066
FC-BGA 1170
October 2014
SR1RB (B3)
SR1X9 (D0)
HD Graphics (4 EUs)
1 × DDR3L-1066
FC-BGA 1170
October 2013
SR1RC (B3)
SR1X8 (D0)
HD Graphics (4 EUs)
533-667 MHz
2 × DDR3L-1066
FC-BGA 1170
October 2013
SR1RD (B3)
SR1X7 (D0)
HD Graphics (4 EUs)
542-792 MHz
2 × DDR3L-1333
FC-BGA 1170
October 2013
All models support: , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), , , .
GPU and memory controller are integrated onto the processor die
GPU is based on
, with 4 execution units, and supports 2 displays, DirectX 11, OpenGL 4.0, OpenGL ES 3.1 and OpenCL 1.1 (on Windows).
Peripherals include
2.0, HD Audio controller,
with 2 ports, , and 4 lanes of
2.0, in x4, x2, and x1 configurations.
Package size: 25 mm × 27 mm
Release date
SR1RE (B3)
SR1X6 (D0)
(4 EUs)
542-792 MHz
1 × DDR3L-1333
FC-BGA 1170
October 2013
All models support: , , , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), , .
GPU and memory controller are integrated onto the processor die
GPU is based on
, with 12 execution units, and supports DirectX 11.2, OpenGL 4.3, OpenGL ES 3.0 and OpenCL 1.2 (on Windows).
Package size: 25 mm × 27 mm
Release date
SR2LV (D1)
(12 EUs)
2 × DDR3L-1600
FC-BGA 1170
January 2016
All Atom server processors include ECC support.
Steppings: B1
Release date
SLK2K (B1)
2 × 512 KB
FC-BGA 1283
December 11, 2012
SLK2J (B1)
2 × 512 KB
FC-BGA 1283
December 11, 2012
SLK2H (B1)
2 × 512 KB
FC-BGA 1283
December 11, 2012
Steppings: B1
Release date
SLK2G (B1)
2 × 512 KB
FC-BGA 1283
SLK2F (B1)
2 × 512 KB
FC-BGA 1283
SLK2E (B1)
2 × 512 KB
FC-BGA 1283
All models support: , , , , , Enhanced Intel
Technology (EIST), ,
(according to Datasheet), XD bit (an
implementation), , , .
peripherals include 4 ×
2.0, 2 × , 2 × Integrated
, 2 × , and 4 lanes of
2.0, in x4, x2, and x1 configurations.
Package size: 34 mm × 28 mm
Release date
SR1CV (B0)
1.7-2.0 GHz
DDR3/3L-1333
FC-BGA 1283
September 2013
All models support: , , , , , Enhanced Intel
Technology (EIST), , , XD bit (an
implementation), , , .
C2308 and C2358 support Intel
Technology (cryptography accelerator)
peripherals include 4 ×
2.0, 4-6 ×
(1 for C2308), 4 × Integrated
, 2 × , and 8 lanes of
2.0 (4 lanes for C2308), in x2 and x1 configurations.
Package size: 34 mm × 28 mm
Release date
SR1UN (B0)
FC-BGA 1283
March 2014
SR1S8 (B0)
1.7-2.0 GHz
DDR3/3L-1333
FC-BGA 1283
September 2013
SR1D2 (B0)
1.7-2.0 GHz
DDR3/3L-1333
FC-BGA 1283
September 2013
All models support: , , , , , Enhanced Intel
Technology (EIST), , , XD bit (an
implementation), , , .
peripherals include 4 ×
2.0, 2 (C2530) or 6 (C2550) × , 2 × Integrated
, 2 × , and 8 lanes of
2.0, in x8, x4, x2, and x1 configurations.
Package size: 34 mm × 28 mm
Release date
SR1CU (B0)
1.7-2.0 GHz
DDR3/3L-1333
FC-BGA 1283
September 2013
SR1CT (B0)
2.4-2.6 GHz
DDR3/3L-1600
FC-BGA 1283
September 2013
All models support: , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), , , .
C2508, C2518, C2558 support Intel
Technology (cryptography accelerator)
peripherals include 4 ×
(2 for C2508), 4 × Integrated
, 2 × , and 16 lanes of
2.0 (8 lanes for C2508), in x16, x8, x4, x2, and x1 configurations.
Package size: 34 mm × 28 mm
Release date
SR1VV (B0)
FC-BGA 1283
March 2014
SR1D1 (B0)
DDR3/3L-1333
FC-BGA 1283
September 2013
SR1S9 (B0)
DDR3/3L-1600
FC-BGA 1283
September 2013
SR1CZ (B0)
DDR3/3L-1600
FC-BGA 1283
September 2013
All models support: , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), , , .
peripherals include 4 ×
2.0, 2 × , 2 × Integrated
, 2 × , and 8 lanes of
2.0, in x8, x4, x2, and x1 configurations.
peripherals include 4 ×
2.0, 6 × , 4 × Integrated
, 2 × , and 16 lanes of
2.0, in x16, x8, x4, x2, and x1 configurations.
Package size: 34 mm × 28 mm
Release date
SR1CR (B0)
1.7-2.0 GHz
DDR3/3L-1333
FC-BGA 1283
September 2013
SR1CS (B0)
2.4-2.6 GHz
DDR3/3L-1600
FC-BGA 1283
September 2013
All models support: , , , , , Enhanced Intel
Technology (EIST), , XD bit (an
implementation), , , .
C2718, C2758 support Intel
Technology (cryptography accelerator)
peripherals include 4 ×
2.0, 6 × , 4 × Integrated
, 2 × , and 16 lanes of
2.0, in x16, x8, x4, x2, and x1 configurations.
Package size: 34 mm × 28 mm
Release date
SR1CY (B0)
DDR3/3L-1333
FC-BGA 1283
September 2013
SR1SA (B0)
DDR3/3L-1600
FC-BGA 1283
September 2013
SR1CW (B0)
DDR3/3L-1600
FC-BGA 1283
September 2013
Package size: 27 mm × 27 mm
GPU (based on the PowerVR SGX535 from Imagination Technologies)
Release date
Atom CE4110
September 24, 2009
Atom CE4130
FC-BGA 951
Atom CE4150
FC-BGA 951
Atom CE4170
FC-BGA 951
Package size: ?? mm × ?? mm
2 × 32-bit memory channels, up to DDR2-800
GPU (based on the PowerVR SGX535 from Imagination Technologies)
Release date
Atom CE4200
2 × DDR2-800
Package size: ?? mm × ?? mm
GPU for 3D (based on the PowerVR SGX545 from Imagination Technologies)
GPU for 2D ( from )
Release date
Atom CE5310
 ? MHz
Atom CE5315
 ? MHz
Atom CE5318
 ? MHz
Atom CE5320
 ? MHz
Atom CE5328
 ? MHz
Atom CE5335
 ? MHz
Atom CE5338
 ? MHz
Atom CE5343
 ? MHz
Atom CE5348
 ? MHz
(A100/A110)
Ganesh T S (11 November 2013). .
Intel (3 February 2014).
, page 61, 63}